msm: msm_sdcc: Add DDR support for eMMC/MMC
If eMMC/MMC cards supports DDR mode, MMC core
layer checks if host controller supports the DDR
mode or not and if host supports the DDR mode,
MMC core layer calls the set_ios to set the
DDR timing mode in host controller.
This change advertise that SDCC4 host controller
supports DDR mode timings and also sets DDR
timing mode when asked in set_ios.
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index 626c11b..20156ee 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -2057,7 +2057,7 @@
};
static unsigned int sdc1_sup_clk_rates[] = {
- 400000, 24000000, 48000000
+ 400000, 24000000, 48000000, 96000000
};
static unsigned int sdc3_sup_clk_rates[] = {
@@ -2077,7 +2077,8 @@
.nonremovable = 1,
.sdcc_v4_sup = true,
.vreg_data = &mmc_slot_vreg_data[SDCC1],
- .pin_data = &mmc_slot_pin_data[SDCC1]
+ .pin_data = &mmc_slot_pin_data[SDCC1],
+ .uhs_caps = MMC_CAP_1_8V_DDR
};
#endif
@@ -2099,7 +2100,7 @@
.xpc_cap = 1,
.uhs_caps = (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 |
- MMC_CAP_MAX_CURRENT_600)
+ MMC_CAP_MAX_CURRENT_600 | MMC_CAP_1_8V_DDR)
};
#endif
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index 7463097..cb96e0d 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -1995,7 +1995,7 @@
* For DDR50 mode, controller needs clock rate to be
* double than what is required on the SD card CLK pin.
*/
- if (ios->timing == MMC_TIMING_UHS_DDR50) {
+ if (ios->ddr || (ios->timing == MMC_TIMING_UHS_DDR50)) {
/*
* Make sure that we don't double the clock if
* doubled clock rate is already set
@@ -2048,7 +2048,7 @@
(ios->timing == MMC_TIMING_UHS_SDR50)) {
clk |= (4 << 14);
host->tuning_needed = 1;
- } else if (ios->timing == MMC_TIMING_UHS_DDR50) {
+ } else if (ios->ddr || ios->timing == MMC_TIMING_UHS_DDR50) {
clk |= (3 << 14);
} else {
clk |= (2 << 14); /* feedback clock */