commit b808efac1fcc2d5027283ed90c0cc5c2a5031d5e
author Subhash Jadavani <subhashj@codeaurora.org> Mon Jun 27 15:14:07 2011 -0700
committer Bryan Huntsman <bryanh@codeaurora.org> Mon Oct 03 10:27:23 2011 -0700
tree be446219d247baed8d9584c124c049bdba5db9b6
parent c9f3509041a4de83c93453e2f39419557f274562

msm: msm_sdcc: Add DDR support for eMMC/MMC

If eMMC/MMC cards supports DDR mode, MMC core
layer checks if host controller supports the DDR
mode or not and if host supports the DDR mode,
MMC core layer calls the set_ios to set the
DDR timing mode in host controller.

This change advertise that SDCC4 host controller
supports DDR mode timings and also sets DDR
timing mode when asked in set_ios.

Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>

arch/arm/mach-msm/board-msm8960.c

diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index 626c11b..20156ee 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -2057,7 +2057,7 @@
 };
 
 static unsigned int sdc1_sup_clk_rates[] = {
-	400000, 24000000, 48000000
+	400000, 24000000, 48000000, 96000000
 };
 
 static unsigned int sdc3_sup_clk_rates[] = {
@@ -2077,7 +2077,8 @@
 	.nonremovable	= 1,
 	.sdcc_v4_sup	= true,
 	.vreg_data	= &mmc_slot_vreg_data[SDCC1],
-	.pin_data	= &mmc_slot_pin_data[SDCC1]
+	.pin_data	= &mmc_slot_pin_data[SDCC1],
+	.uhs_caps	= MMC_CAP_1_8V_DDR
 };
 #endif
 
@@ -2099,7 +2100,7 @@
 	.xpc_cap	= 1,
 	.uhs_caps	= (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
 			MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 |
-			MMC_CAP_MAX_CURRENT_600)
+			MMC_CAP_MAX_CURRENT_600 | MMC_CAP_1_8V_DDR)
 };
 #endif