ARM: EXYNOS4: Add support clock for EXYNOS4412
This patch makes EXYNOS4412 use same clock code for
EXYNOS4212 because the clock hierarchy of both SoCs
are same.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index f26aea3..2a037cc 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -1149,7 +1149,7 @@
if (soc_is_exynos4210())
return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
pll_4508);
- else if (soc_is_exynos4212())
+ else if (soc_is_exynos4212() || soc_is_exynos4412())
return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
else
return 0;
@@ -1200,7 +1200,7 @@
vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
__raw_readl(S5P_VPLL_CON1), pll_4650c);
- } else if (soc_is_exynos4212()) {
+ } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),