crypto: Fix Cipher Test Failures
This patch fixes 2 issues that was causing cipher operation
failure
(1) Status register reflecting an SW_ERR (ACCESS_VIOL bit set)
Status register needed to be cleared initially before
starting any operation
(2) Occasional failure observed in some cipher operation(s)
(encryption and/or decryption) for modes that require
reading in the CNTR IV register values after an
operation is complete.
These failures show up when doing a 3DES-CBC operation.
But there is potential for it to raise its head when doing
DES-CBC, AES-CBC or AES_XTS modes as well (since all of this
modes require reading in the CNTR IV register).
The CNTR IV register was being read after writing data to
the IN FIFO. There is a potential for encryption (or decryption)
operations to not have completed fully on all the data in the FIFO
before the IV register is read, resulting in incorrect IV value.
The fix is to read the CNTR IV register after the operation
is guranteed to have completed sucessfully. This is done after
reading data out of DATA OUT FIFO.
Change-Id: Icef0d544ecb463cea4be978c3d2809049b92da05
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
diff --git a/drivers/crypto/msm/qce40.h b/drivers/crypto/msm/qce40.h
index c9fbb17..809ba7f 100644
--- a/drivers/crypto/msm/qce40.h
+++ b/drivers/crypto/msm/qce40.h
@@ -117,6 +117,7 @@
/* CE Command lists */
struct ce_cmdlists {
dmov_s *get_hw_version;
+ dmov_s *clear_status;
dmov_s *get_status_ocu;
dmov_s *set_cipher_cfg;
@@ -132,10 +133,8 @@
dmov_s *set_cipher_aes_iv;
dmov_s *set_cipher_aes_xts_iv;
- dmov_s *get_cipher_aes_iv;
- dmov_s *get_cipher_aes_xts_iv;
dmov_s *set_cipher_des_iv;
- dmov_s *get_cipher_des_iv;
+ dmov_s *get_cipher_iv;
dmov_s *set_cipher_mask;
@@ -195,6 +194,7 @@
uint32_t aead_aes_256_ccm;
uint32_t cipher_ce_out;
+ uint32_t cipher_ce_out_get_iv;
uint32_t aead_ce_out;
};