msm: pm-boot: Modify PM warmboot sequence instructions
Due to a h/w bug on 8625 once cores come out of the low
power mode(GDFS) and immediately executing the first
"ldr" instruction causes the fetching of improper value
from the memory. This causes the aborts on cores. This
patch adds few memory read instrucitons before it actually
jump to the warmboot entry function.
Change-Id: I76d1228878f3a5ea1179d51d043e0ebf1b92d2bc
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
diff --git a/arch/arm/mach-msm/board-msm7x27a.c b/arch/arm/mach-msm/board-msm7x27a.c
index c91f2b6..28d1cf0 100644
--- a/arch/arm/mach-msm/board-msm7x27a.c
+++ b/arch/arm/mach-msm/board-msm7x27a.c
@@ -950,7 +950,7 @@
{
msm7x27a_reserve();
memblock_remove(MSM8625_SECONDARY_PHYS, SZ_8);
- msm_pm_8625_boot_pdata.p_addr = memblock_alloc(SZ_8, SZ_64K);
+ msm_pm_8625_boot_pdata.p_addr = memblock_alloc(SZ_16, SZ_64K);
}
static void __init msm7x27a_device_i2c_init(void)
diff --git a/arch/arm/mach-msm/pm-boot.c b/arch/arm/mach-msm/pm-boot.c
index f4536f7..f65b8ad 100644
--- a/arch/arm/mach-msm/pm-boot.c
+++ b/arch/arm/mach-msm/pm-boot.c
@@ -144,8 +144,17 @@
} else {
entry = virt_to_phys(msm_pm_boot_entry);
- msm_pm_reset_vector[0] = 0xE51FF004; /* ldr pc, 4 */
- msm_pm_reset_vector[1] = entry;
+ /* Below sequence is a work around for cores
+ * to come out of GDFS properly on 8625 target.
+ * On 8625 while cores coming out of GDFS observed
+ * the memory corruption at very first memory read.
+ */
+ msm_pm_reset_vector[0] = 0xE59F000C; /* ldr r0, 0x14 */
+ msm_pm_reset_vector[1] = 0xE59F1008; /* ldr r1, 0x14 */
+ msm_pm_reset_vector[2] = 0xE1500001; /* cmp r0, r1 */
+ msm_pm_reset_vector[3] = 0x1AFFFFFB; /* bne 0x0 */
+ msm_pm_reset_vector[4] = 0xE12FFF10; /* bx r0 */
+ msm_pm_reset_vector[5] = entry; /* 0x14 */
/* Here upper 16bits[16:31] used by CORE1
* lower 16bits[0:15] used by CORE0