msm: kgsl: Enable GPUMMU protection for IOMMU registers on older chips
For older chips we protect the IOMMU registers by mapping them
in a GPUMMU range that is only made visible to the GPU when we
actually program the IOMMU registers using in stream commands. This
protection method is used for older chips because it does not
support IOMMU context bank switching.
Change-Id: I58f8b4f397e2e4c4ec181097257f1ff63683c074
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c
index 6a86ea3..fdd4aa5 100644
--- a/drivers/gpu/msm/kgsl_iommu.c
+++ b/drivers/gpu/msm/kgsl_iommu.c
@@ -24,6 +24,7 @@
#include "kgsl_sharedmem.h"
#include "kgsl_iommu.h"
#include "adreno_pm4types.h"
+#include "adreno.h"
/*
* kgsl_iommu_disable_clk - Disable iommu clocks
@@ -587,16 +588,24 @@
if (status)
return -ENOMEM;
}
- kgsl_regwrite(mmu->device, MH_MMU_CONFIG, 0x00000000);
+ /* We use the GPU MMU to control access to IOMMU registers on a225,
+ * hence we still keep the MMU active on a225 */
+ if (adreno_is_a225(ADRENO_DEVICE(mmu->device))) {
+ struct kgsl_mh *mh = &(mmu->device->mh);
+ kgsl_regwrite(mmu->device, MH_MMU_CONFIG, 0x00000001);
+ kgsl_regwrite(mmu->device, MH_MMU_MPU_END,
+ mh->mpu_base +
+ iommu->iommu_units[0].reg_map.gpuaddr - PAGE_SIZE);
+ } else {
+ kgsl_regwrite(mmu->device, MH_MMU_CONFIG, 0x00000000);
+ }
mmu->hwpagetable = mmu->defaultpagetable;
status = kgsl_attach_pagetable_iommu_domain(mmu);
- if (!status) {
- mmu->flags |= KGSL_FLAGS_STARTED;
- } else {
- kgsl_detach_pagetable_iommu_domain(mmu);
+ if (status) {
mmu->hwpagetable = NULL;
+ goto done;
}
status = kgsl_iommu_enable_clk(mmu, KGSL_IOMMU_CONTEXT_USER);
if (status) {
@@ -628,6 +637,7 @@
CONTEXTIDR);
kgsl_iommu_disable_clk(mmu);
+ mmu->flags |= KGSL_FLAGS_STARTED;
done:
if (status) {
@@ -708,6 +718,7 @@
*/
if (mmu->flags & KGSL_FLAGS_STARTED) {
+ kgsl_regwrite(mmu->device, MH_MMU_CONFIG, 0x00000000);
/* detach iommu attachment */
kgsl_detach_pagetable_iommu_domain(mmu);
mmu->hwpagetable = NULL;