)]}'
{
  "commit": "bf0f2e23834e2bf7d64b467ef07095b1c7e2c04b",
  "tree": "0a652a8e4cc51f50139d892cee17f7a699c4afa4",
  "parents": [
    "8e0d4f4e9132ae6e353f9cf27261627bcc7c65cc"
  ],
  "author": {
    "name": "Paolo \u0027Blaisorblade\u0027 Giarrusso",
    "email": "blaisorblade@yahoo.it",
    "time": "Sat Nov 05 17:25:54 2005 +0100"
  },
  "committer": {
    "name": "Linus Torvalds",
    "email": "torvalds@g5.osdl.org",
    "time": "Mon Nov 14 19:55:17 2005 -0800"
  },
  "message": "[PATCH] x86_64: Set ____cacheline_maxaligned_in_smp alignment to 128 bytes\n\nThe current value was correct before the introduction of Intel EM64T support -\nbut now L1_CACHE_SHIFT_MAX can be less than L1_CACHE_SHIFT, which _is_ funny!\n\nBetween the few users of ____cacheline_maxaligned_in_smp, we also have (for\nexample) rcu_ctrlblk, and struct zone, with zone-\u003e{lru_,}lock.  I.e.  we have\na lot of excess cacheline bouncing on them.\n\nNo correctness issues, obviously.  So this could even be merged for 2.6.14\n(I\u0027m not a fan of this idea, though).\n\nCC: Andi Kleen \u003cak@suse.de\u003e\nSigned-off-by: Paolo \u0027Blaisorblade\u0027 Giarrusso \u003cblaisorblade@yahoo.it\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Andi Kleen \u003cak@suse.de\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "eda62bae1240366bd83ad33f6e97284cca260d66",
      "old_mode": 33188,
      "old_path": "include/asm-x86_64/cache.h",
      "new_id": "33e53424128b33a4096162bfe29848b2885a8b16",
      "new_mode": 33188,
      "new_path": "include/asm-x86_64/cache.h"
    }
  ]
}