commit c0978205fe9786b0a49e9e7c599f761f1afa3ac7
author Jordan Crouse <jcrouse@codeaurora.org> Wed Aug 29 14:35:51 2012 -0600
committer Rajeev Kulkarni <krajeev@codeaurora.org> Wed Nov 21 22:11:37 2012 -0800
tree 8bc8f1d66d0b2f4c1da3b54295d36389a26f2d91
parent cf3252d5c65282c356a67988fb025afd5482c76c

msm: kgsl: Add adreno_is_a330() for A330 specific code

Create adreno_is_a330() to identify the GPU for A330 specific
register settings and core specific code.

Change-Id: Ic0dedbade244ffba3ba3917661a88f97108e6182
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>

drivers/gpu/msm/adreno_a3xx.c

diff --git a/drivers/gpu/msm/adreno_a3xx.c b/drivers/gpu/msm/adreno_a3xx.c
index 4b3263d..ba7160f 100644
--- a/drivers/gpu/msm/adreno_a3xx.c
+++ b/drivers/gpu/msm/adreno_a3xx.c
@@ -2698,7 +2698,7 @@
 	struct kgsl_device *device = &adreno_dev->dev;
 
 	/* Set up 16 deep read/write request queues */
-	if (adreno_dev->gpurev == ADRENO_REV_A330) {
+	if (adreno_is_a330(adreno_dev)) {
 		adreno_regwrite(device, A3XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);
 		adreno_regwrite(device, A3XX_VBIF_IN_RD_LIM_CONF1, 0x18181818);
 		adreno_regwrite(device, A3XX_VBIF_OUT_RD_LIM_CONF0, 0x18181818);
@@ -2781,7 +2781,7 @@
 			A3XX_RBBM_CLOCK_CTL_DEFAULT);
 
 	/* Set the OCMEM base address for A330 */
-	if (adreno_dev->gpurev == ADRENO_REV_A330) {
+	if (adreno_is_a330(adreno_dev)) {
 		adreno_regwrite(device, A3XX_RB_GMEM_BASE_ADDR,
 			(unsigned int)(adreno_dev->ocmem_base >> 14));
 	}