commit c0b5b1b24148873787019a60de0555df1fd1f8f1
author Sameer Thalappil <sameert@codeaurora.org> Thu Nov 29 14:10:48 2012 -0800
committer Sameer Thalappil <sameert@codeaurora.org> Thu Mar 07 16:30:06 2013 -0800
tree 309505037b9840217e6c7cedc7d27031382bbf67
parent 01643d56d90f4373585250464169b866ea6b2911

wcnss: Configure bite interrupt as edge triggered

Riva bite interrupt is edge triggered

CRs-Fixed: 422014
Change-Id: Ie51d65763e11e4d9de55d7b0fe5a07b910c114e6
Signed-off-by: Sameer Thalappil <sameert@codeaurora.org>

arch/arm/mach-msm/wcnss-ssr-8960.c

diff --git a/arch/arm/mach-msm/wcnss-ssr-8960.c b/arch/arm/mach-msm/wcnss-ssr-8960.c
index 8bc58f0..b302866 100644
--- a/arch/arm/mach-msm/wcnss-ssr-8960.c
+++ b/arch/arm/mach-msm/wcnss-ssr-8960.c
@@ -237,7 +237,7 @@
 		goto out;
 	}
 	ret = request_irq(RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ,
-			riva_wdog_bite_irq_hdlr, IRQF_TRIGGER_HIGH,
+			riva_wdog_bite_irq_hdlr, IRQF_TRIGGER_RISING,
 				"riva_wdog", NULL);
 
 	if (ret < 0) {