msm: clock: Remove warned flag
Now that all clock consumers have moved over to using the
clk_prepare/unprepare APIs we can remove the warned flag that
used to indicate that we had already warned about improper usage
of the clock APIs. In particular, we used this flag to avoid
printing warnings for "source" clocks such as PLLs and
crystals that no consumer directly controls but that the clock
driver calls clk_enable() on during clk_set_rate().
Let's use a local variable for clk->dbg_name too because we use
it many times and it makes lines too long.
Change-Id: I0cb3052fd3dec2e46788fbf039ac73f65551e9f9
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index f3ac7d7..8cce34b 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -239,7 +239,6 @@
.rate = 19200000,
.ops = &clk_ops_tcxo,
CLK_INIT(tcxo_clk.c),
- .warned = true,
},
};
@@ -266,7 +265,6 @@
.rate = 24576000,
.ops = &clk_ops_lpxo,
CLK_INIT(lpxo_clk.c),
- .warned = true,
},
};
@@ -281,7 +279,6 @@
.rate = 768000000,
.ops = &clk_ops_pll_vote,
CLK_INIT(pll1_clk.c),
- .warned = true,
},
};
@@ -296,7 +293,6 @@
.rate = 806400000, /* TODO: Support scaling */
.ops = &clk_ops_pll_vote,
CLK_INIT(pll2_clk.c),
- .warned = true,
},
};
@@ -325,7 +321,6 @@
.rate = 891000000,
.ops = &clk_ops_pll_vote,
CLK_INIT(pll4_clk.c),
- .warned = true,
},
};
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index f46821f..8e586a5 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -519,7 +519,6 @@
.rate = 800000000,
.ops = &clk_ops_local_pll,
CLK_INIT(pll2_clk.c),
- .warned = true,
},
};
@@ -533,7 +532,6 @@
.vdd_class = &vdd_sr2_hdmi_pll,
.fmax[VDD_SR2_HDMI_PLL_ON] = ULONG_MAX,
CLK_INIT(pll3_clk.c),
- .warned = true,
},
};
@@ -548,7 +546,6 @@
.rate = 393216000,
.ops = &clk_ops_pll_vote,
CLK_INIT(pll4_clk.c),
- .warned = true,
},
};
@@ -563,7 +560,6 @@
.rate = 384000000,
.ops = &clk_ops_pll_vote,
CLK_INIT(pll8_clk.c),
- .warned = true,
},
};
@@ -578,7 +574,6 @@
.rate = 480000000,
.ops = &clk_ops_pll_vote,
CLK_INIT(pll14_clk.c),
- .warned = true,
},
};
@@ -590,7 +585,6 @@
.rate = 975000000,
.ops = &clk_ops_local_pll,
CLK_INIT(pll15_clk.c),
- .warned = true,
},
};
@@ -2731,7 +2725,6 @@
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csi0_src_clk.c),
- .warned = true,
},
};
@@ -2749,7 +2742,6 @@
.dbg_name = "csi0_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi0_clk.c),
- .warned = true,
},
};
@@ -2789,7 +2781,6 @@
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csi1_src_clk.c),
- .warned = true,
},
};
@@ -2807,7 +2798,6 @@
.dbg_name = "csi1_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi1_clk.c),
- .warned = true,
},
};
@@ -2847,7 +2837,6 @@
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csi2_src_clk.c),
- .warned = true,
},
};
@@ -2865,7 +2854,6 @@
.dbg_name = "csi2_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi2_clk.c),
- .warned = true,
},
};
diff --git a/arch/arm/mach-msm/clock-8974.c b/arch/arm/mach-msm/clock-8974.c
index ce45008..afa854c 100644
--- a/arch/arm/mach-msm/clock-8974.c
+++ b/arch/arm/mach-msm/clock-8974.c
@@ -687,7 +687,6 @@
.rate = 600000000,
.dbg_name = "gpll0_clk_src",
.ops = &clk_ops_pll_vote,
- .warned = true,
CLK_INIT(gpll0_clk_src.c),
},
};
@@ -703,7 +702,6 @@
.rate = 480000000,
.dbg_name = "gpll1_clk_src",
.ops = &clk_ops_pll_vote,
- .warned = true,
CLK_INIT(gpll1_clk_src.c),
},
};
@@ -719,7 +717,6 @@
.rate = 491520000,
.dbg_name = "lpapll0_clk_src",
.ops = &clk_ops_pll_vote,
- .warned = true,
CLK_INIT(lpapll0_clk_src.c),
},
};
@@ -735,7 +732,6 @@
.dbg_name = "mmpll0_clk_src",
.rate = 800000000,
.ops = &clk_ops_pll_vote,
- .warned = true,
CLK_INIT(mmpll0_clk_src.c),
},
};
@@ -751,7 +747,6 @@
.dbg_name = "mmpll1_clk_src",
.rate = 846000000,
.ops = &clk_ops_pll_vote,
- .warned = true,
CLK_INIT(mmpll1_clk_src.c),
},
};
@@ -765,7 +760,6 @@
.dbg_name = "mmpll3_clk_src",
.rate = 1000000000,
.ops = &clk_ops_local_pll,
- .warned = true,
CLK_INIT(mmpll3_clk_src.c),
},
};
@@ -3001,7 +2995,6 @@
.dbg_name = "hdmipll_clk_src",
.ops = &clk_ops_hdmi_pll,
CLK_INIT(hdmipll_clk_src),
- .warned = true,
};
static struct clk_freq_tbl ftbl_mdss_extpclk_clk[] = {
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 609db6e..677053a 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -313,7 +313,6 @@
.rate = 384000000,
.ops = &clk_ops_pll_vote,
CLK_INIT(pll8_clk.c),
- .warned = true,
},
};
@@ -325,7 +324,6 @@
.rate = 800000000,
.ops = &clk_ops_local_pll,
CLK_INIT(pll2_clk.c),
- .warned = true,
},
};
@@ -337,7 +335,6 @@
.rate = 0, /* TODO: Detect rate dynamically */
.ops = &clk_ops_local_pll,
CLK_INIT(pll3_clk.c),
- .warned = true,
},
};
@@ -387,7 +384,6 @@
.rate = 540672000,
.ops = &clk_ops_pll4,
CLK_INIT(pll4_clk.c),
- .warned = true,
},
};
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index 1574d9c..15eaa4b 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -272,7 +272,6 @@
.rate = 276000000,
.ops = &clk_ops_pll_acpu_vote,
CLK_INIT(pll0_clk.c),
- .warned = true,
},
};
@@ -288,7 +287,6 @@
.rate = 276000000,
.ops = &clk_ops_pll_acpu_vote,
CLK_INIT(pll0_activeonly_clk.c),
- .warned = true,
},
};
@@ -303,7 +301,6 @@
.rate = 393216000,
.ops = &clk_ops_pll_vote,
CLK_INIT(pll4_clk.c),
- .warned = true,
},
};
@@ -322,7 +319,6 @@
.rate = 384000000,
.ops = &clk_ops_pll_acpu_vote,
CLK_INIT(pll8_clk.c),
- .warned = true,
},
};
@@ -338,7 +334,6 @@
.rate = 384000000,
.ops = &clk_ops_pll_acpu_vote,
CLK_INIT(pll8_activeonly_clk.c),
- .warned = true,
},
};
@@ -349,7 +344,6 @@
.rate = 440000000,
.ops = &clk_ops_local_pll,
CLK_INIT(pll9_activeonly_clk.c),
- .warned = true,
},
};
@@ -364,7 +358,6 @@
.rate = 480000000,
.ops = &clk_ops_pll_vote,
CLK_INIT(pll14_clk.c),
- .warned = true,
},
};
diff --git a/arch/arm/mach-msm/clock-rpm.h b/arch/arm/mach-msm/clock-rpm.h
index e203028..7952a33 100644
--- a/arch/arm/mach-msm/clock-rpm.h
+++ b/arch/arm/mach-msm/clock-rpm.h
@@ -110,7 +110,6 @@
.dbg_name = #name, \
.rate = (r), \
CLK_INIT(name.c), \
- .warned = true, \
}, \
}; \
static struct rpm_clk active = { \
@@ -129,7 +128,6 @@
.dbg_name = #active, \
.rate = (r), \
CLK_INIT(active.c), \
- .warned = true, \
}, \
};
@@ -148,7 +146,6 @@
.ops = &clk_ops_rpm, \
.dbg_name = #name, \
CLK_INIT(name.c), \
- .warned = true, \
}, \
}; \
static struct rpm_clk active = { \
@@ -164,7 +161,6 @@
.ops = &clk_ops_rpm, \
.dbg_name = #active, \
CLK_INIT(active.c), \
- .warned = true, \
}, \
};
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index 6a3a282..2b7a4f5 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -198,6 +198,7 @@
int ret = 0;
unsigned long flags;
struct clk *parent;
+ const char *name = clk ? clk->dbg_name : NULL;
if (!clk)
return 0;
@@ -205,10 +206,8 @@
return -EINVAL;
spin_lock_irqsave(&clk->lock, flags);
- if (WARN(!clk->warned && !clk->prepare_count,
- "%s: Don't call enable on unprepared clocks\n",
- clk->dbg_name))
- clk->warned = true;
+ WARN(!clk->prepare_count,
+ "%s: Don't call enable on unprepared clocks\n", name);
if (clk->count == 0) {
parent = clk_get_parent(clk);
@@ -219,7 +218,7 @@
if (ret)
goto err_enable_depends;
- trace_clock_enable(clk->dbg_name, 1, smp_processor_id());
+ trace_clock_enable(name, 1, smp_processor_id());
if (clk->ops->enable)
ret = clk->ops->enable(clk);
if (ret)
@@ -242,23 +241,22 @@
void clk_disable(struct clk *clk)
{
+ const char *name = clk ? clk->dbg_name : NULL;
unsigned long flags;
if (IS_ERR_OR_NULL(clk))
return;
spin_lock_irqsave(&clk->lock, flags);
- if (WARN(!clk->warned && !clk->prepare_count,
- "%s: Never called prepare or calling disable "
- "after unprepare\n",
- clk->dbg_name))
- clk->warned = true;
- if (WARN(clk->count == 0, "%s is unbalanced", clk->dbg_name))
+ WARN(!clk->prepare_count,
+ "%s: Never called prepare or calling disable after unprepare\n",
+ name);
+ if (WARN(clk->count == 0, "%s is unbalanced", name))
goto out;
if (clk->count == 1) {
struct clk *parent = clk_get_parent(clk);
- trace_clock_disable(clk->dbg_name, 0, smp_processor_id());
+ trace_clock_disable(name, 0, smp_processor_id());
if (clk->ops->disable)
clk->ops->disable(clk);
clk_disable(clk->depends);
@@ -272,23 +270,20 @@
void clk_unprepare(struct clk *clk)
{
+ const char *name = clk ? clk->dbg_name : NULL;
+
if (IS_ERR_OR_NULL(clk))
return;
mutex_lock(&clk->prepare_lock);
- if (!clk->prepare_count) {
- if (WARN(!clk->warned, "%s is unbalanced (prepare)",
- clk->dbg_name))
- clk->warned = true;
+ if (WARN(!clk->prepare_count, "%s is unbalanced (prepare)", name))
goto out;
- }
if (clk->prepare_count == 1) {
struct clk *parent = clk_get_parent(clk);
- if (WARN(!clk->warned && clk->count,
+ WARN(clk->count,
"%s: Don't call unprepare when the clock is enabled\n",
- clk->dbg_name))
- clk->warned = true;
+ name);
if (clk->ops->unprepare)
clk->ops->unprepare(clk);
@@ -330,6 +325,7 @@
{
unsigned long start_rate;
int rc = 0;
+ const char *name = clk ? clk->dbg_name : NULL;
if (IS_ERR_OR_NULL(clk))
return -EINVAL;
@@ -343,7 +339,7 @@
if (clk->rate == rate)
goto out;
- trace_clock_set_rate(clk->dbg_name, rate, raw_smp_processor_id());
+ trace_clock_set_rate(name, rate, raw_smp_processor_id());
if (clk->prepare_count) {
start_rate = clk->rate;
/* Enforce vdd requirements for target frequency. */
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 4e3d83b..45d2f71 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -114,7 +114,6 @@
* @depends: non-direct parent of clock to enable when this clock is enabled
* @vdd_class: voltage scaling requirement class
* @fmax: maximum frequency in Hz supported at each voltage level
- * @warned: true if the clock has warned of incorrect usage, false otherwise
*/
struct clk {
uint32_t flags;
@@ -128,7 +127,6 @@
struct list_head children;
struct list_head siblings;
- bool warned;
unsigned count;
spinlock_t lock;
unsigned prepare_count;