commit c4559f67b73d6c34fde0faac5c6c890a2cf3527c
author Maciej W. Rozycki <macro@linux-mips.org> Thu Jun 23 15:57:15 2005 +0000
committer Ralf Baechle <ralf@linux-mips.org> Sat Oct 29 19:31:31 2005 +0100
tree 4063b3a937215684db85cc4f70eabd99cf3b8573
parent 69c75fb458cd81bb29e1d9580469110b00316748

Always use ".set mips3" rather than select between "mips2" or "mips3"
for assembling ll/sc sequences to avoid problems with 64-bit
configurations.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

arch/mips/kernel/semaphore.c

diff --git a/arch/mips/kernel/semaphore.c b/arch/mips/kernel/semaphore.c
index dbb145e..1265358 100644
--- a/arch/mips/kernel/semaphore.c
+++ b/arch/mips/kernel/semaphore.c
@@ -42,7 +42,7 @@
 
 	if (cpu_has_llsc && R10000_LLSC_WAR) {
 		__asm__ __volatile__(
-		"	.set	mips2					\n"
+		"	.set	mips3					\n"
 		"1:	ll	%0, %2		# __sem_update_count	\n"
 		"	sra	%1, %0, 31				\n"
 		"	not	%1					\n"
@@ -55,7 +55,7 @@
 		: "r" (incr), "m" (sem->count));
 	} else if (cpu_has_llsc) {
 		__asm__ __volatile__(
-		"	.set	mips2					\n"
+		"	.set	mips3					\n"
 		"1:	ll	%0, %2		# __sem_update_count	\n"
 		"	sra	%1, %0, 31				\n"
 		"	not	%1					\n"