)]}'
{
  "commit": "c5cf0e30bf3d8cb56758abb612827647c0a821cf",
  "tree": "54a471818e91204db11f14544df0bb38bd03058f",
  "parents": [
    "a5bba930d802009c259e56c8d53086d96f63813b"
  ],
  "author": {
    "name": "Benjamin Herrenschmidt",
    "email": "benh@au1.ibm.com",
    "time": "Tue May 30 14:14:19 2006 +1000"
  },
  "committer": {
    "name": "Paul Mackerras",
    "email": "paulus@samba.org",
    "time": "Fri Jun 09 21:20:59 2006 +1000"
  },
  "message": "[PATCH] powerpc: Fix buglet with MMU hash management\n\nOur MMU hash management code would not set the \"C\" bit (changed bit) in\nthe hardware PTE when updating a RO PTE into a RW PTE. That would cause\nthe hardware to possibly to a write back to the hash table to set it on\nthe first store access, which in addition to being a performance issue,\nmight also hit a bug when running with native hash management (non-HV)\nas our code is specifically optimized for the case where no write back\nhappens.\n\nThus there is a very small therocial window were a hash PTE can become\ncorrupted if that HPTE has just been upgraded to read write, a store\naccess happens on it, and that races with another processor evicting\nthat same slot. Since eviction (caused by an almost full hash) is\nextremely rare, the bug is very unlikely to happen fortunately.\n\nThis fixes by allowing the updating of the protection bits in the native\nhash handling to also set (but not clear) the \"C\" bit, and, in order to\nalso improve performances in the general case, by always setting that\nbit on newly inserted hash PTE so that writeback really never happens.\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Paul Mackerras \u003cpaulus@samba.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e0d02c4a2615f8787abc1b13737f7b78e67bc5a5",
      "old_mode": 33188,
      "old_path": "arch/powerpc/mm/hash_low_64.S",
      "new_id": "106fba391987376ce8c3599e610aa86cfe484674",
      "new_mode": 33188,
      "new_path": "arch/powerpc/mm/hash_low_64.S"
    },
    {
      "type": "modify",
      "old_id": "33654d1b1b43b596ac70e98cf834a1185157f355",
      "old_mode": 33188,
      "old_path": "arch/powerpc/mm/hash_native_64.c",
      "new_id": "3b8205033f15379c9e2a0cfb8f3c98056004d67e",
      "new_mode": 33188,
      "new_path": "arch/powerpc/mm/hash_native_64.c"
    },
    {
      "type": "modify",
      "old_id": "96e47d1ce97920c53c218c10c554d761147c7ff5",
      "old_mode": 33188,
      "old_path": "include/asm-powerpc/mmu.h",
      "new_id": "8853974201046cc2a1535b3127fcb3344887bea8",
      "new_mode": 33188,
      "new_path": "include/asm-powerpc/mmu.h"
    }
  ]
}