[ARM] 3832/1: iop3xx: coding style cleanup
Since the iop32x code isn't iop321-specific, and the iop33x code isn't
iop331-specfic, do a s/iop321/iop32x/ and s/iop331/iop33x/, and tidy up
the code to conform to the coding style guidelines somewhat better.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index ff049e0..21294be 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -1,5 +1,5 @@
/*
- * linux/arch/arm/mach-iop32x/irq.c
+ * arch/arm/mach-iop32x/irq.c
*
* Generic IOP32X IRQ handling functionality
*
@@ -9,76 +9,66 @@
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
- *
- * Added IOP3XX chipset and IQ80321 board masking code.
- *
*/
+
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/list.h>
-
#include <asm/mach/irq.h>
#include <asm/irq.h>
#include <asm/hardware.h>
-
#include <asm/mach-types.h>
-static u32 iop321_mask /* = 0 */;
+static u32 iop32x_mask;
static inline void intctl_write(u32 val)
{
iop3xx_cp6_enable();
- asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
+ asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
}
static inline void intstr_write(u32 val)
{
iop3xx_cp6_enable();
- asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val));
+ asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
}
static void
-iop321_irq_mask (unsigned int irq)
+iop32x_irq_mask(unsigned int irq)
{
-
- iop321_mask &= ~(1 << irq);
-
- intctl_write(iop321_mask);
+ iop32x_mask &= ~(1 << irq);
+ intctl_write(iop32x_mask);
}
static void
-iop321_irq_unmask (unsigned int irq)
+iop32x_irq_unmask(unsigned int irq)
{
- iop321_mask |= (1 << irq);
-
- intctl_write(iop321_mask);
+ iop32x_mask |= 1 << irq;
+ intctl_write(iop32x_mask);
}
struct irq_chip ext_chip = {
- .name = "IOP",
- .ack = iop321_irq_mask,
- .mask = iop321_irq_mask,
- .unmask = iop321_irq_unmask,
+ .name = "IOP32x",
+ .ack = iop32x_irq_mask,
+ .mask = iop32x_irq_mask,
+ .unmask = iop32x_irq_unmask,
};
-void __init iop321_init_irq(void)
+void __init iop32x_init_irq(void)
{
- unsigned int i;
+ int i;
- intctl_write(0); // disable all interrupts
- intstr_write(0); // treat all as IRQ
- if(machine_is_iq80321() ||
- machine_is_iq31244()) // all interrupts are inputs to chip
+ intctl_write(0);
+ intstr_write(0);
+ if (machine_is_iq80321() ||
+ machine_is_iq31244())
*IOP3XX_PCIIRSR = 0x0f;
- for(i = 0; i < NR_IRQS; i++)
- {
+ for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &ext_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-
}
}
-