msm: iommu: Remove the vcap iommu from 8960ab.
There is no vcap iommu in the 8960ab platform.
Also, a cleaner separation between platforms is
obtained by re-organizing the gfx3d and vcap
structures by device block instead of by msm.
Signed-off-by: Joel King <joelking@codeaurora.org>
(cherry picked from commit b82921f43be2debbe59738a96fe4332b7b48f6b6)
Change-Id: I044842db17a59f6df1328674a5d65931313dead2
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
diff --git a/arch/arm/mach-msm/devices-iommu.c b/arch/arm/mach-msm/devices-iommu.c
index ae8a8fe..b65bd1f 100644
--- a/arch/arm/mach-msm/devices-iommu.c
+++ b/arch/arm/mach-msm/devices-iommu.c
@@ -939,8 +939,11 @@
&msm_device_iommu_gfx2d1,
};
-static struct platform_device *msm_iommu_8064_devs[] = {
+static struct platform_device *msm_iommu_adreno3xx_gfx_devs[] = {
&msm_device_iommu_gfx3d1,
+};
+
+static struct platform_device *msm_iommu_vcap_devs[] = {
&msm_device_iommu_vcap,
};
@@ -973,9 +976,12 @@
&msm_device_gfx2d1_2d1_ctx,
};
-static struct platform_device *msm_iommu_8064_ctx_devs[] = {
+static struct platform_device *msm_iommu_adreno3xx_ctx_devs[] = {
&msm_device_gfx3d1_user_ctx,
&msm_device_gfx3d1_priv_ctx,
+};
+
+static struct platform_device *msm_iommu_vcap_ctx_devs[] = {
&msm_device_vcap_vc_ctx,
&msm_device_vcap_vp_ctx,
};
@@ -1014,9 +1020,12 @@
if (cpu_is_apq8064() || cpu_is_msm8960ab()) {
platform_add_devices(msm_iommu_jpegd_devs,
ARRAY_SIZE(msm_iommu_jpegd_devs));
- platform_add_devices(msm_iommu_8064_devs,
- ARRAY_SIZE(msm_iommu_8064_devs));
+ platform_add_devices(msm_iommu_adreno3xx_gfx_devs,
+ ARRAY_SIZE(msm_iommu_adreno3xx_gfx_devs));
}
+ if (cpu_is_apq8064())
+ platform_add_devices(msm_iommu_vcap_devs,
+ ARRAY_SIZE(msm_iommu_vcap_devs));
/* Initialize common ctx_devs */
ret = platform_add_devices(msm_iommu_common_ctx_devs,
@@ -1033,9 +1042,13 @@
if (cpu_is_apq8064() || cpu_is_msm8960ab()) {
platform_add_devices(msm_iommu_jpegd_ctx_devs,
ARRAY_SIZE(msm_iommu_jpegd_ctx_devs));
- platform_add_devices(msm_iommu_8064_ctx_devs,
- ARRAY_SIZE(msm_iommu_8064_ctx_devs));
+
+ platform_add_devices(msm_iommu_adreno3xx_ctx_devs,
+ ARRAY_SIZE(msm_iommu_adreno3xx_ctx_devs));
}
+ if (cpu_is_apq8064())
+ platform_add_devices(msm_iommu_vcap_ctx_devs,
+ ARRAY_SIZE(msm_iommu_vcap_ctx_devs));
return 0;
@@ -1068,16 +1081,33 @@
for (i = 0; i < ARRAY_SIZE(msm_iommu_jpegd_devs); i++)
platform_device_unregister(msm_iommu_jpegd_devs[i]);
}
+ if (cpu_is_apq8064()) {
+ for (i = 0; i < ARRAY_SIZE(msm_iommu_vcap_ctx_devs); i++)
+ platform_device_unregister(msm_iommu_vcap_ctx_devs[i]);
+ }
if (cpu_is_apq8064() || cpu_is_msm8960ab()) {
- for (i = 0; i < ARRAY_SIZE(msm_iommu_8064_ctx_devs); i++)
- platform_device_unregister(msm_iommu_8064_ctx_devs[i]);
+ for (i = 0; i < ARRAY_SIZE(msm_iommu_adreno3xx_ctx_devs);
+ i++)
+ platform_device_unregister(
+ msm_iommu_adreno3xx_ctx_devs[i]);
- for (i = 0; i < ARRAY_SIZE(msm_iommu_jpegd_ctx_devs); i++)
- platform_device_unregister(msm_iommu_jpegd_ctx_devs[i]);
+ for (i = 0; i < ARRAY_SIZE(msm_iommu_jpegd_ctx_devs);
+ i++)
+ platform_device_unregister(
+ msm_iommu_jpegd_ctx_devs[i]);
- for (i = 0; i < ARRAY_SIZE(msm_iommu_8064_devs); i++)
- platform_device_unregister(msm_iommu_8064_devs[i]);
+ if (cpu_is_apq8064()) {
+ for (i = 0; i < ARRAY_SIZE(msm_iommu_vcap_devs);
+ i++)
+ platform_device_unregister(
+ msm_iommu_vcap_devs[i]);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(msm_iommu_adreno3xx_gfx_devs);
+ i++)
+ platform_device_unregister(
+ msm_iommu_adreno3xx_gfx_devs[i]);
for (i = 0; i < ARRAY_SIZE(msm_iommu_jpegd_devs); i++)
platform_device_unregister(msm_iommu_jpegd_devs[i]);