ARM: vmlinux.lds.S: Align sections to correct cache line size
Align sections to the selected cache line size rather than
assuming a line size of 32 bytes.
Change-Id: Ib8a30cc5abd66036c0fd7366bcdad07dc1047c04
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 8d71217..7f7e5c0 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -196,12 +196,12 @@
NOSAVE_DATA
CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
- READ_MOSTLY_DATA(32)
+ READ_MOSTLY_DATA(L1_CACHE_BYTES)
/*
* The exception fixup table (might need resorting at runtime)
*/
- . = ALIGN(32);
+ . = ALIGN(L1_CACHE_BYTES);
__start___ex_table = .;
#ifdef CONFIG_MMU
*(__ex_table)