msm: kgsl: Update A3XX REG_TO_MEM opcodes in legacy context switch
Version 29 of the PM4 firmware for A3XX modified the format of the
REG_TO_MEM opcode by changing the bit shift of one the fields.
Modify the legacy context switch code accordingly. This will break
users of older firmware, but the old firmware shouldn't ever be in
wide use anyway, so backwards compatibility is not a concern.
Change-Id: Ic0dedbad9a6d50077a0001c95d2a0dcd30c4f070
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
diff --git a/drivers/gpu/msm/adreno_a3xx.c b/drivers/gpu/msm/adreno_a3xx.c
index f68bc41..1585db10 100644
--- a/drivers/gpu/msm/adreno_a3xx.c
+++ b/drivers/gpu/msm/adreno_a3xx.c
@@ -130,7 +130,7 @@
/* Use shadow RAM */
#define HLSQ_SHADOW_BASE (0x10000+SSIZE*2)
-#define REG_TO_MEM_LOOP_COUNT_SHIFT 15
+#define REG_TO_MEM_LOOP_COUNT_SHIFT 18
#define BUILD_PC_DRAW_INITIATOR(prim_type, source_select, index_size, \
vis_cull_mode) \
@@ -1109,11 +1109,13 @@
/* Constant save */
cmd = rmw_regtomem(cmd, A3XX_SP_VS_CTRL_REG1, 0x000003ff,
- 17, (HLSQ_SHADOW_BASE + 0x2000) / 4,
+ 2 + REG_TO_MEM_LOOP_COUNT_SHIFT,
+ (HLSQ_SHADOW_BASE + 0x2000) / 4,
drawctxt->constant_save_commands[1].gpuaddr);
cmd = rmw_regtomem(cmd, A3XX_SP_FS_CTRL_REG1, 0x000003ff,
- 17, (HLSQ_SHADOW_BASE + 0x2000 + SSIZE) / 4,
+ 2 + REG_TO_MEM_LOOP_COUNT_SHIFT,
+ (HLSQ_SHADOW_BASE + 0x2000 + SSIZE) / 4,
drawctxt->constant_save_commands[2].gpuaddr);
cmd = rmw_regtomem(cmd, A3XX_SP_FS_OBJ_OFFSET_REG, 0x00ff0000,