MIPS: TXx9: Cache fixup
TX39/TX49 can enable/disable I/D cache at runtime. Add kernel options
to control them. This is useful to debug some cache-related issues,
such as aliasing or I/D coherency. Also enable CWF bit for TX49 SoCs.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c
index 87db41b..2e40a92 100644
--- a/arch/mips/txx9/jmr3927/setup.c
+++ b/arch/mips/txx9/jmr3927/setup.c
@@ -62,7 +62,6 @@
}
#define DO_WRITE_THROUGH
-#define DO_ENABLE_CACHE
static void jmr3927_board_init(void);
@@ -77,11 +76,6 @@
/* cache setup */
{
unsigned int conf;
-#ifdef DO_ENABLE_CACHE
- int mips_ic_disable = 0, mips_dc_disable = 0;
-#else
- int mips_ic_disable = 1, mips_dc_disable = 1;
-#endif
#ifdef DO_WRITE_THROUGH
int mips_config_cwfon = 0;
int mips_config_wbon = 0;
@@ -91,10 +85,7 @@
#endif
conf = read_c0_conf();
- conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE |
- TX39_CONF_WBON | TX39_CONF_CWFON);
- conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
- conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
+ conf &= ~(TX39_CONF_WBON | TX39_CONF_CWFON);
conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;