)]}'
{
  "commit": "d1c038d620c45fbbc65bcadf813a86bca686dd31",
  "tree": "7041ac78c80e58f43fb507c209608d8a3bab7756",
  "parents": [
    "353e5019e048562dc8f434c6237d41ef5e758922"
  ],
  "author": {
    "name": "Senthil Balasubramanian",
    "email": "senthilkumar@atheros.com",
    "time": "Fri Apr 22 11:32:09 2011 +0530"
  },
  "committer": {
    "name": "John W. Linville",
    "email": "linville@tuxdriver.com",
    "time": "Mon Apr 25 14:50:17 2011 -0400"
  },
  "message": "ath9k_hw: Fix incorrect baseband PLL phase shift for AR9485\n\nwe should program the AR9485 baseband PLL phase shift to 6 and\na redundant setting overwrites the correct value. Remove the\nincorrect and unwnated register setting.\n\nSigned-off-by: Senthil Balasubramanian \u003csenthilkumar@atheros.com\u003e\nSigned-off-by: John W. Linville \u003clinville@tuxdriver.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "577ca59b02bf68c5a437c6d17ac0dc0d59475a11",
      "old_mode": 33188,
      "old_path": "drivers/net/wireless/ath/ath9k/hw.c",
      "new_id": "6166ba0bca54bb10e7763676cc2ced5c26ecd315",
      "new_mode": 33188,
      "new_path": "drivers/net/wireless/ath/ath9k/hw.c"
    }
  ]
}