)]}'
{
  "commit": "d387a8d66670371e6be3b6d6bde2e38b8cade076",
  "tree": "988a0d0898779694f4299886d7b72607a5b4fdea",
  "parents": [
    "086ac11f6435c9dc2fe5025fc8ea3a1dbca273d6"
  ],
  "author": {
    "name": "Jon Mason",
    "email": "mason@myri.com",
    "time": "Fri Oct 14 14:56:13 2011 -0500"
  },
  "committer": {
    "name": "Jesse Barnes",
    "email": "jbarnes@virtuousgeek.org",
    "time": "Thu Oct 27 12:45:42 2011 -0700"
  },
  "message": "PCI: Workaround for Intel MPS errata\n\nIntel 5000 and 5100 series memory controllers have a known issue if read\ncompletion coalescing is enabled and the PCI-E Maximum Payload Size is\nset to 256B.  To work around this issue, disable read completion\ncoalescing in the memory controller and root complexes.  Unfortunately,\nit must always be disabled, even if no 256B MPS devices are present, due\nto the possibility of one being hotplugged.\n\nLinks to erratas:\nhttp://www.intel.com/content/dam/doc/specification-update/5000-chipset-memory-controller-hub-specification-update.pdf\nhttp://www.intel.com/content/dam/doc/specification-update/5100-memory-controller-hub-chipset-specification-update.pdf\n\nThanks to Jesse Brandeburg and Ben Hutchings for providing insight into\nthe problem.\n\nTested-and-Reported-by: Avi Kivity \u003cavi@redhat.com\u003e\nSigned-off-by: Jon Mason \u003cmason@myri.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e5aadf357ae795c3163875ea25375658822ad7f5",
      "old_mode": 33188,
      "old_path": "drivers/pci/quirks.c",
      "new_id": "dca58b9ba8c6b1033175039bf6b6d4fef2e7d964",
      "new_mode": 33188,
      "new_path": "drivers/pci/quirks.c"
    }
  ]
}