msm: platsmp: Update Krait reset sequence
The SMP CPU initialization code incorrectly applied the
KPSS 2.x CPU reset sequence to Krait Pass 3, even on
targets using KPSS 1.x. Modify the SMP code to apply the
KPSS 1.x reset sequence where appropriate, regardless of
the CPU version. Also incorporate updated register settings
to avoid having to later reconfigure the Krait PLL clamps.
CRs-Fixed: 431744
Change-Id: I41b07fa96e95bdc23ba742f6f4a9fcea70a10a7a
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 01e203f..aca1fb1 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -102,26 +102,24 @@
msm_spm_turn_on_cpu_rail(cpu);
- if (cpu_is_krait_v1() || cpu_is_krait_v2()) {
- writel_relaxed(0x109, base_ptr+0x04);
- writel_relaxed(0x101, base_ptr+0x04);
- mb();
- ndelay(300);
- writel_relaxed(0x121, base_ptr+0x04);
- } else
- writel_relaxed(0x021, base_ptr+0x04);
+ writel_relaxed(0x109, base_ptr+0x04);
+ writel_relaxed(0x101, base_ptr+0x04);
+ mb();
+ ndelay(300);
+
+ writel_relaxed(0x121, base_ptr+0x04);
mb();
udelay(2);
- writel_relaxed(0x020, base_ptr+0x04);
+ writel_relaxed(0x120, base_ptr+0x04);
mb();
udelay(2);
- writel_relaxed(0x000, base_ptr+0x04);
+ writel_relaxed(0x100, base_ptr+0x04);
mb();
udelay(100);
- writel_relaxed(0x080, base_ptr+0x04);
+ writel_relaxed(0x180, base_ptr+0x04);
mb();
iounmap(base_ptr);
return 0;