)]}'
{
  "commit": "d58577d8f36f66dbb5dec30fc01dfddda0cfd1fa",
  "tree": "92840d18b50ccaa63fbc4aec85c962223c5e9982",
  "parents": [
    "dc568ec4906ac2478e2d692adc6b12fbb6e4657e"
  ],
  "author": {
    "name": "John Linn",
    "email": "john.linn@xilinx.com",
    "time": "Wed Jul 02 15:11:28 2008 -0700"
  },
  "committer": {
    "name": "Grant Likely",
    "email": "grant.likely@secretlab.ca",
    "time": "Fri Jul 04 00:58:59 2008 -0600"
  },
  "message": "powerpc/virtex: Fix booting of Xilinx FPGAs with 16550 for 405 and 440\n\nThe following changes add processing to initialize the Xilinx 16550 UART\nin the boot wrapper for Virtex targets without firmware.  Normally the\nboot wrapper assumes that the serial port has already been initialized by\nfirmware.\n\nThe wrapper was also modified to add the 440 build.\n\nSigned-off-by: John Linn \u003cjohn.linn@xilinx.com\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "arch/powerpc/boot/Makefile",
      "new_id": "df6e62116e37097444422277fac0dbee670da218",
      "new_mode": 33188,
      "new_path": "arch/powerpc/boot/Makefile"
    },
    {
      "type": "modify",
      "old_id": "86cd285bccc6b2c32e53ec82dffb81aa5b90a815",
      "old_mode": 33188,
      "old_path": "arch/powerpc/boot/simpleboot.c",
      "new_id": "c58a0dada992eef1c9edd4d901a6c9901fba413a",
      "new_mode": 33188,
      "new_path": "arch/powerpc/boot/simpleboot.c"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "f622805f8000cdaf1934902f5390b6a8a090ffd3",
      "new_mode": 33188,
      "new_path": "arch/powerpc/boot/virtex.c"
    },
    {
      "type": "modify",
      "old_id": "df2358e9f1ca7eef060e5a8a564ddfbc3ab80592",
      "old_mode": 33261,
      "old_path": "arch/powerpc/boot/wrapper",
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      "new_mode": 33261,
      "new_path": "arch/powerpc/boot/wrapper"
    }
  ]
}