msm: acpuclock-7201: Add delay for apps cpu clock switch
While changing the apps cpu clock source, it takes some
time till the clock switch is complete. After clock switch
is complete, then only loops per jiffies must be updated.
Earlier we are updating the loops per jiffies before the
clock switch is complete, which in turn lead to wrong BOGO
MIPS value for that duration for time.
Hence add the delay at appropriate place.
Change-Id: Ide6c7a7dcc5c679b5178420c69691b70ed699a18
Signed-off-by: Pankaj Kumar <pakuma@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-7201.c b/arch/arm/mach-msm/acpuclock-7201.c
index ec71565..b6c0b26 100644
--- a/arch/arm/mach-msm/acpuclock-7201.c
+++ b/arch/arm/mach-msm/acpuclock-7201.c
@@ -468,6 +468,10 @@
reg_clksel ^= 1;
writel_relaxed(reg_clksel, A11S_CLK_SEL_ADDR);
+ /* Wait for the clock switch to complete */
+ mb();
+ udelay(50);
+
/*
* If the new clock divider is lower than the previous, then
* program the divider after switching the clock
@@ -619,8 +623,6 @@
/* Adjust the global one */
loops_per_jiffy = cur_s->lpj;
- mb();
- udelay(50);
}
/* Nothing else to do for SWFI. */