msm: acpuclock-8960: Fix regulator-related debug prints
Regulator names are not printed in all regulator-related debug messages.
Fix this and remove the duplicate __func__ prefix for these messages.
Also, the regulator names 'krait0_dig' and 'krait0_mem' were assigned for
all CPUs, not just Krait 0. Change this so the number in the regulator
name matches the CPU number the regulator is associated with.
Change-Id: I1843d30670c44434f8f190a2b8d7fda71c308357
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-8960.c b/arch/arm/mach-msm/acpuclock-8960.c
index 4ea36a0..99c3d78 100644
--- a/arch/arm/mach-msm/acpuclock-8960.c
+++ b/arch/arm/mach-msm/acpuclock-8960.c
@@ -148,10 +148,10 @@
.vreg[VREG_DIG] = { "krait0_dig", 1150000,
RPM_VREG_VOTER1,
RPM_VREG_ID_PM8921_S3 },
- .vreg[VREG_HFPLL_A] = { "hfpll", 2100000,
+ .vreg[VREG_HFPLL_A] = { "hfpll0_s8", 2100000,
RPM_VREG_VOTER1,
RPM_VREG_ID_PM8921_S8 },
- .vreg[VREG_HFPLL_B] = { "hfpll", 1800000,
+ .vreg[VREG_HFPLL_B] = { "hfpll0_l23", 1800000,
RPM_VREG_VOTER1,
RPM_VREG_ID_PM8921_L23 },
},
@@ -160,16 +160,16 @@
.aux_clk_sel = MSM_ACC1_BASE + 0x014,
.l2cpmr_iaddr = L2CPUCPMR_IADDR,
.vreg[VREG_CORE] = { "krait1", 1300000 },
- .vreg[VREG_MEM] = { "krait0_mem", 1150000,
+ .vreg[VREG_MEM] = { "krait1_mem", 1150000,
RPM_VREG_VOTER2,
RPM_VREG_ID_PM8921_L24 },
- .vreg[VREG_DIG] = { "krait0_dig", 1150000,
+ .vreg[VREG_DIG] = { "krait1_dig", 1150000,
RPM_VREG_VOTER2,
RPM_VREG_ID_PM8921_S3 },
- .vreg[VREG_HFPLL_A] = { "hfpll", 2100000,
+ .vreg[VREG_HFPLL_A] = { "hfpll1_s8", 2100000,
RPM_VREG_VOTER2,
RPM_VREG_ID_PM8921_S8 },
- .vreg[VREG_HFPLL_B] = { "hfpll", 1800000,
+ .vreg[VREG_HFPLL_B] = { "hfpll1_l23", 1800000,
RPM_VREG_VOTER2,
RPM_VREG_ID_PM8921_L23 },
},
@@ -177,10 +177,10 @@
.hfpll_base = MSM_HFPLL_BASE + 0x400,
.aux_clk_sel = MSM_APCS_GCC_BASE + 0x028,
.l2cpmr_iaddr = L2CPMR_IADDR,
- .vreg[VREG_HFPLL_A] = { "hfpll", 2100000,
+ .vreg[VREG_HFPLL_A] = { "hfpll_l2_s8", 2100000,
RPM_VREG_VOTER6,
RPM_VREG_ID_PM8921_S8 },
- .vreg[VREG_HFPLL_B] = { "hfpll", 1800000,
+ .vreg[VREG_HFPLL_B] = { "hfpll_l2_l23", 1800000,
RPM_VREG_VOTER6,
RPM_VREG_ID_PM8921_L23 },
},
@@ -201,7 +201,7 @@
.vreg[VREG_DIG] = { "krait0_dig", 1150000,
RPM_VREG_VOTER1,
RPM_VREG_ID_PM8921_S3 },
- .vreg[VREG_HFPLL_B] = { "hfpll", 1800000,
+ .vreg[VREG_HFPLL_B] = { "hfpll0", 1800000,
RPM_VREG_VOTER1,
RPM_VREG_ID_PM8921_LVS7 },
},
@@ -210,13 +210,13 @@
.aux_clk_sel = MSM_ACC1_BASE + 0x014,
.l2cpmr_iaddr = L2CPUCPMR_IADDR,
.vreg[VREG_CORE] = { "krait1", 1150000 },
- .vreg[VREG_MEM] = { "krait0_mem", 1150000,
+ .vreg[VREG_MEM] = { "krait1_mem", 1150000,
RPM_VREG_VOTER2,
RPM_VREG_ID_PM8921_L24 },
- .vreg[VREG_DIG] = { "krait0_dig", 1150000,
+ .vreg[VREG_DIG] = { "krait1_dig", 1150000,
RPM_VREG_VOTER2,
RPM_VREG_ID_PM8921_S3 },
- .vreg[VREG_HFPLL_B] = { "hfpll", 1800000,
+ .vreg[VREG_HFPLL_B] = { "hfpll1", 1800000,
RPM_VREG_VOTER2,
RPM_VREG_ID_PM8921_LVS7 },
},
@@ -225,13 +225,13 @@
.aux_clk_sel = MSM_ACC2_BASE + 0x014,
.l2cpmr_iaddr = L2CPUCPMR_IADDR,
.vreg[VREG_CORE] = { "krait2", 1150000 },
- .vreg[VREG_MEM] = { "krait0_mem", 1150000,
+ .vreg[VREG_MEM] = { "krait2_mem", 1150000,
RPM_VREG_VOTER4,
RPM_VREG_ID_PM8921_L24 },
- .vreg[VREG_DIG] = { "krait0_dig", 1150000,
+ .vreg[VREG_DIG] = { "krait2_dig", 1150000,
RPM_VREG_VOTER4,
RPM_VREG_ID_PM8921_S3 },
- .vreg[VREG_HFPLL_B] = { "hfpll", 1800000,
+ .vreg[VREG_HFPLL_B] = { "hfpll2", 1800000,
RPM_VREG_VOTER4,
RPM_VREG_ID_PM8921_LVS7 },
},
@@ -240,13 +240,13 @@
.aux_clk_sel = MSM_ACC3_BASE + 0x014,
.l2cpmr_iaddr = L2CPUCPMR_IADDR,
.vreg[VREG_CORE] = { "krait3", 1150000 },
- .vreg[VREG_MEM] = { "krait0_mem", 1150000,
+ .vreg[VREG_MEM] = { "krait3_mem", 1150000,
RPM_VREG_VOTER5,
RPM_VREG_ID_PM8921_L24 },
- .vreg[VREG_DIG] = { "krait0_dig", 1150000,
+ .vreg[VREG_DIG] = { "krait3_dig", 1150000,
RPM_VREG_VOTER5,
RPM_VREG_ID_PM8921_S3 },
- .vreg[VREG_HFPLL_B] = { "hfpll", 1800000,
+ .vreg[VREG_HFPLL_B] = { "hfpll3", 1800000,
RPM_VREG_VOTER5,
RPM_VREG_ID_PM8921_LVS7 },
},
@@ -254,7 +254,7 @@
.hfpll_base = MSM_HFPLL_BASE + 0x300,
.aux_clk_sel = MSM_APCS_GCC_BASE + 0x028,
.l2cpmr_iaddr = L2CPMR_IADDR,
- .vreg[VREG_HFPLL_B] = { "hfpll", 1800000,
+ .vreg[VREG_HFPLL_B] = { "hfpll_l2", 1800000,
RPM_VREG_VOTER6,
RPM_VREG_ID_PM8921_LVS7 },
},
@@ -272,7 +272,7 @@
.vreg[VREG_DIG] = { "krait0_dig", 1150000,
RPM_VREG_VOTER1,
RPM_VREG_ID_PM8038_S1 },
- .vreg[VREG_HFPLL_B] = { "hfpll", 1800000,
+ .vreg[VREG_HFPLL_B] = { "hfpll0", 1800000,
RPM_VREG_VOTER1,
RPM_VREG_ID_PM8038_L23 },
},
@@ -281,13 +281,13 @@
.aux_clk_sel = MSM_ACC1_BASE + 0x014,
.l2cpmr_iaddr = L2CPUCPMR_IADDR,
.vreg[VREG_CORE] = { "krait1", 1300000 },
- .vreg[VREG_MEM] = { "krait0_mem", 1150000,
+ .vreg[VREG_MEM] = { "krait1_mem", 1150000,
RPM_VREG_VOTER2,
RPM_VREG_ID_PM8038_L24 },
- .vreg[VREG_DIG] = { "krait0_dig", 1150000,
+ .vreg[VREG_DIG] = { "krait1_dig", 1150000,
RPM_VREG_VOTER2,
RPM_VREG_ID_PM8038_S1 },
- .vreg[VREG_HFPLL_B] = { "hfpll", 1800000,
+ .vreg[VREG_HFPLL_B] = { "hfpll1", 1800000,
RPM_VREG_VOTER2,
RPM_VREG_ID_PM8038_L23 },
},
@@ -295,7 +295,7 @@
.hfpll_base = MSM_HFPLL_BASE + 0x400,
.aux_clk_sel = MSM_APCS_GCC_BASE + 0x028,
.l2cpmr_iaddr = L2CPMR_IADDR,
- .vreg[VREG_HFPLL_B] = { "hfpll", 1800000,
+ .vreg[VREG_HFPLL_B] = { "hfpll_l2", 1800000,
RPM_VREG_VOTER6,
RPM_VREG_ID_PM8038_L23 },
},
@@ -314,7 +314,7 @@
.vreg[VREG_DIG] = { "krait0_dig", 1150000,
RPM_VREG_VOTER1,
RPM_VREG_ID_PM8038_S1 },
- .vreg[VREG_HFPLL_B] = { "hfpll", 1800000,
+ .vreg[VREG_HFPLL_B] = { "hfpll0", 1800000,
RPM_VREG_VOTER1,
RPM_VREG_ID_PM8038_L23 },
},
@@ -323,13 +323,13 @@
.aux_clk_sel = MSM_ACC1_BASE + 0x014,
.l2cpmr_iaddr = L2CPUCPMR_IADDR,
.vreg[VREG_CORE] = { "krait1", 1300000 },
- .vreg[VREG_MEM] = { "krait0_mem", 1150000,
+ .vreg[VREG_MEM] = { "krait1_mem", 1150000,
RPM_VREG_VOTER2,
RPM_VREG_ID_PM8038_L24 },
- .vreg[VREG_DIG] = { "krait0_dig", 1150000,
+ .vreg[VREG_DIG] = { "krait1_dig", 1150000,
RPM_VREG_VOTER2,
RPM_VREG_ID_PM8038_S1 },
- .vreg[VREG_HFPLL_B] = { "hfpll", 1800000,
+ .vreg[VREG_HFPLL_B] = { "hfpll1", 1800000,
RPM_VREG_VOTER2,
RPM_VREG_ID_PM8038_L23 },
},
@@ -337,7 +337,7 @@
.hfpll_base = MSM_HFPLL_BASE + 0x400,
.aux_clk_sel = MSM_APCS_GCC_BASE + 0x028,
.l2cpmr_iaddr = L2CPMR_IADDR,
- .vreg[VREG_HFPLL_B] = { "hfpll", 1800000,
+ .vreg[VREG_HFPLL_B] = { "hfpll_l2", 1800000,
RPM_VREG_VOTER6,
RPM_VREG_ID_PM8038_L23 },
},
@@ -922,8 +922,8 @@
sc->vreg[VREG_MEM].rpm_vreg_voter, vdd_mem,
sc->vreg[VREG_MEM].max_vdd, 0);
if (rc) {
- pr_err("%s: vdd_mem (cpu%d) increase failed (%d)\n",
- __func__, cpu, rc);
+ pr_err("%s increase failed (%d)\n",
+ sc->vreg[VREG_MEM].name, rc);
return rc;
}
sc->vreg[VREG_MEM].cur_vdd = vdd_mem;
@@ -935,8 +935,8 @@
sc->vreg[VREG_DIG].rpm_vreg_voter, vdd_dig,
sc->vreg[VREG_DIG].max_vdd, 0);
if (rc) {
- pr_err("%s: vdd_dig (cpu%d) increase failed (%d)\n",
- __func__, cpu, rc);
+ pr_err("%s increase failed (%d)\n",
+ sc->vreg[VREG_DIG].name, rc);
return rc;
}
sc->vreg[VREG_DIG].cur_vdd = vdd_dig;
@@ -953,8 +953,8 @@
rc = regulator_set_voltage(sc->vreg[VREG_CORE].reg, vdd_core,
sc->vreg[VREG_CORE].max_vdd);
if (rc) {
- pr_err("%s: vdd_core (cpu%d) increase failed (%d)\n",
- __func__, cpu, rc);
+ pr_err("%s increase failed (%d)\n",
+ sc->vreg[VREG_CORE].name, rc);
return rc;
}
sc->vreg[VREG_CORE].cur_vdd = vdd_core;
@@ -980,8 +980,8 @@
ret = regulator_set_voltage(sc->vreg[VREG_CORE].reg, vdd_core,
sc->vreg[VREG_CORE].max_vdd);
if (ret) {
- pr_err("%s: vdd_core (cpu%d) decrease failed (%d)\n",
- __func__, cpu, ret);
+ pr_err("%s decrease failed (%d)\n",
+ sc->vreg[VREG_CORE].name, ret);
return;
}
sc->vreg[VREG_CORE].cur_vdd = vdd_core;
@@ -993,8 +993,8 @@
sc->vreg[VREG_DIG].rpm_vreg_voter, vdd_dig,
sc->vreg[VREG_DIG].max_vdd, 0);
if (ret) {
- pr_err("%s: vdd_dig (cpu%d) decrease failed (%d)\n",
- __func__, cpu, ret);
+ pr_err("%s decrease failed (%d)\n",
+ sc->vreg[VREG_DIG].name, ret);
return;
}
sc->vreg[VREG_DIG].cur_vdd = vdd_dig;
@@ -1009,8 +1009,8 @@
sc->vreg[VREG_MEM].rpm_vreg_voter, vdd_mem,
sc->vreg[VREG_MEM].max_vdd, 0);
if (ret) {
- pr_err("%s: vdd_mem (cpu%d) decrease failed (%d)\n",
- __func__, cpu, ret);
+ pr_err("%s decrease failed (%d)\n",
+ sc->vreg[VREG_MEM].name, ret);
return;
}
sc->vreg[VREG_MEM].cur_vdd = vdd_mem;