)]}'
{
  "commit": "da30e0ac0f9a521f0cfec8145ddd1ad131f66d61",
  "tree": "4a9002e6fca4d4763b40908403fc177153b9a6a8",
  "parents": [
    "f91e2c3bd427239c198351f44814dd39db91afe0"
  ],
  "author": {
    "name": "Catalin Marinas",
    "email": "catalin.marinas@arm.com",
    "time": "Tue Dec 07 16:56:29 2010 +0100"
  },
  "committer": {
    "name": "Russell King",
    "email": "rmk+kernel@arm.linux.org.uk",
    "time": "Sun Dec 12 23:25:58 2010 +0000"
  },
  "message": "ARM: 6528/1: Use CTR for the I-cache line size on ARMv7\n\nThe current implementation of the v7_coherent_*_range function assumes\nthat the D and I cache lines have the same size, which is incorrect\narchitecturally. This patch adds the icache_line_size macro which reads\nthe CTR register. The main loop in v7_coherent_*_range is split in two\nindependent loops or the D and I caches. This also has the performance\nadvantage that the DSB is moved outside the main loop.\n\nReported-by: Kevin Sapp \u003cksapp@quicinc.com\u003e\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a3ebf7a4f49b2b404da115a58e7fdf6923792625",
      "old_mode": 33188,
      "old_path": "arch/arm/mm/cache-v7.S",
      "new_id": "6136e68ce953d038ef0fa92b8211a3c477ef8e83",
      "new_mode": 33188,
      "new_path": "arch/arm/mm/cache-v7.S"
    },
    {
      "type": "modify",
      "old_id": "321555b894d1d665fe8441ea8dc50772232a0abc",
      "old_mode": 33188,
      "old_path": "arch/arm/mm/proc-macros.S",
      "new_id": "b795afd0a2c620ad1e8f774b1c166bc8639b2847",
      "new_mode": 33188,
      "new_path": "arch/arm/mm/proc-macros.S"
    }
  ]
}