)]}'
{
  "commit": "db0d4db22a78d31c59087f7057b8f1612fecc35d",
  "tree": "e2d84ee2c816d4bef066806863a3937792a08581",
  "parents": [
    "cfcfc9eca2bcbd26a8e206baeb005b055dbf8e37"
  ],
  "author": {
    "name": "Marc Zyngier",
    "email": "marc.zyngier@arm.com",
    "time": "Sat Nov 12 16:09:49 2011 +0000"
  },
  "committer": {
    "name": "Marc Zyngier",
    "email": "marc.zyngier@arm.com",
    "time": "Tue Nov 15 18:13:03 2011 +0000"
  },
  "message": "ARM: gic: allow GIC to support non-banked setups\n\nThe GIC support code is heavily using the fact that hardware\nimplementations are exposing banked registers. Unfortunately, it\nlooks like at least one GIC implementation (EXYNOS) offers both\nthe distributor and the CPU interfaces at different addresses,\ndepending on the CPU.\n\nThis problem is solved by allowing the distributor and CPU interface\naddresses to be per-cpu variables for the platforms that require it.\nThe EXYNOS code is updated not to mess with the GIC internals while\nhandling interrupts, and struct gic_chip_data is back to being private.\nThe DT binding for the gic is updated to allow an optional \"cpu-offset\"\nvalue, which is used to compute the various base addresses.\n\nFinally, a new config option (GIC_NON_BANKED) is used to control this\nfeature, so the overhead is only present on kernels compiled with\nsupport for EXYNOS.\n\nTested on Origen (EXYNOS4) and Panda (OMAP4).\n\nCc: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\nCc: Will Deacon \u003cwill.deacon@arm.com\u003e\nCc: Thomas Abraham \u003cthomas.abraham@linaro.org\u003e\nAcked-by: Rob Herring \u003crob.herring@calxeda.com\u003e\nSigned-off-by: Marc Zyngier \u003cmarc.zyngier@arm.com\u003e\n",
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