msm: kgsl: Use the new clock naming conventions effectively
Still allow the clocks a per-platform map for clock error checking,
but use a const array of their identical names.
Change-Id: If83654b4cf68b34f0cbde68021c267aceb423db8
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index e1e922e..fd3da76 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -4201,10 +4201,8 @@
if (SOCINFO_VERSION_MAJOR(soc_platform_version) == 1) {
struct kgsl_device_platform_data *kgsl_3d0_pdata =
msm_kgsl_3d0.dev.platform_data;
- kgsl_3d0_pdata->pwr_data.pwrlevel[0].gpu_freq =
- 320000000;
- kgsl_3d0_pdata->pwr_data.pwrlevel[1].gpu_freq =
- 266667000;
+ kgsl_3d0_pdata->pwrlevel[0].gpu_freq = 320000000;
+ kgsl_3d0_pdata->pwrlevel[1].gpu_freq = 266667000;
}
}
diff --git a/arch/arm/mach-msm/devices-8960.c b/arch/arm/mach-msm/devices-8960.c
index 0a300ad..2add8f9 100644
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -2052,52 +2052,41 @@
};
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 400000000,
- .bus_freq = 4,
- .io_fraction = 0,
- },
- {
- .gpu_freq = 300000000,
- .bus_freq = 3,
- .io_fraction = 33,
- },
- {
- .gpu_freq = 200000000,
- .bus_freq = 2,
- .io_fraction = 100,
- },
- {
- .gpu_freq = 128000000,
- .bus_freq = 1,
- .io_fraction = 100,
- },
- {
- .gpu_freq = 27000000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 400000000,
+ .bus_freq = 4,
+ .io_fraction = 0,
},
- .init_level = 0,
- .num_levels = 5,
- .set_grp_async = NULL,
- .idle_timeout = HZ/5,
- .nap_allowed = true,
+ {
+ .gpu_freq = 300000000,
+ .bus_freq = 3,
+ .io_fraction = 33,
+ },
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 2,
+ .io_fraction = 100,
+ },
+ {
+ .gpu_freq = 128000000,
+ .bus_freq = 1,
+ .io_fraction = 100,
+ },
+ {
+ .gpu_freq = 27000000,
+ .bus_freq = 0,
+ },
},
- .clk = {
- .name = {
- .clk = "core_clk",
- .pclk = "iface_clk",
- },
+ .init_level = 0,
+ .num_levels = 5,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/5,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM_IFACE,
#ifdef CONFIG_MSM_BUS_SCALING
- .bus_scale_table = &grp3d_bus_scale_pdata,
+ .bus_scale_table = &grp3d_bus_scale_pdata,
#endif
- },
- .imem_clk_name = {
- .clk = NULL,
- .pclk = "mem_iface_clk",
- },
.iommu_user_ctx_name = "gfx3d_user",
.iommu_priv_ctx_name = NULL,
};
@@ -2128,33 +2117,25 @@
};
static struct kgsl_device_platform_data kgsl_2d0_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 200000000,
- .bus_freq = 1,
- },
- {
- .gpu_freq = 200000000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 1,
},
- .init_level = 0,
- .num_levels = 2,
- .set_grp_async = NULL,
- .idle_timeout = HZ/10,
- .nap_allowed = true,
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 0,
+ },
},
- .clk = {
- .name = {
- /* note: 2d clocks disabled on v1 */
- .clk = "core_clk",
- .pclk = "iface_clk",
- },
+ .init_level = 0,
+ .num_levels = 2,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/10,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE,
#ifdef CONFIG_MSM_BUS_SCALING
- .bus_scale_table = &grp2d0_bus_scale_pdata,
+ .bus_scale_table = &grp2d0_bus_scale_pdata,
#endif
- },
.iommu_user_ctx_name = "gfx2d0_2d0",
.iommu_priv_ctx_name = NULL,
};
@@ -2185,32 +2166,25 @@
};
static struct kgsl_device_platform_data kgsl_2d1_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 200000000,
- .bus_freq = 1,
- },
- {
- .gpu_freq = 200000000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 1,
},
- .init_level = 0,
- .num_levels = 2,
- .set_grp_async = NULL,
- .idle_timeout = HZ/10,
- .nap_allowed = true,
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 0,
+ },
},
- .clk = {
- .name = {
- .clk = "core_clk",
- .pclk = "iface_clk",
- },
+ .init_level = 0,
+ .num_levels = 2,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/10,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE,
#ifdef CONFIG_MSM_BUS_SCALING
- .bus_scale_table = &grp2d1_bus_scale_pdata,
+ .bus_scale_table = &grp2d1_bus_scale_pdata,
#endif
- },
.iommu_user_ctx_name = "gfx2d1_2d1",
.iommu_priv_ctx_name = NULL,
};
diff --git a/arch/arm/mach-msm/devices-msm7x27.c b/arch/arm/mach-msm/devices-msm7x27.c
index 1bb9a21..0fb64dc 100644
--- a/arch/arm/mach-msm/devices-msm7x27.c
+++ b/arch/arm/mach-msm/devices-msm7x27.c
@@ -807,32 +807,22 @@
};
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
- .pwr_data = {
- /* bus_freq has been set to 160000 for power savings.
- * OEMs may modify the value at their discretion for performance
- * The appropriate maximum replacement for 160000 is:
- * msm7x2x_clock_data.max_axi_khz
- */
- .pwrlevel = {
- {
- .gpu_freq = 0,
- .bus_freq = 160000000,
- },
- },
- .init_level = 0,
- .num_levels = 1,
- .set_grp_async = NULL,
- .idle_timeout = HZ/5,
- },
- .clk = {
- .name = {
- .clk = "core_clk",
- .pclk = "iface_clk",
+ /* bus_freq has been set to 160000 for power savings.
+ * OEMs may modify the value at their discretion for performance
+ * The appropriate maximum replacement for 160000 is:
+ * msm7x2x_clock_data.max_axi_khz
+ */
+ .pwrlevel = {
+ {
+ .gpu_freq = 0,
+ .bus_freq = 160000000,
},
},
- .imem_clk_name = {
- .clk = "mem_clk",
- },
+ .init_level = 0,
+ .num_levels = 1,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/5,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM,
};
struct platform_device msm_kgsl_3d0 = {
diff --git a/arch/arm/mach-msm/devices-msm7x27a.c b/arch/arm/mach-msm/devices-msm7x27a.c
index 7008bd5..2b08098 100644
--- a/arch/arm/mach-msm/devices-msm7x27a.c
+++ b/arch/arm/mach-msm/devices-msm7x27a.c
@@ -588,34 +588,22 @@
};
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 245760000,
- .bus_freq = 200000000,
- },
- {
- .gpu_freq = 133330000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 245760000,
+ .bus_freq = 200000000,
},
- .init_level = 0,
- .num_levels = 2,
- .set_grp_async = set_grp_xbar_async,
- .idle_timeout = HZ/5,
- .nap_allowed = false,
- },
- .clk = {
- .name = {
- .clk = "core_clk",
- .pclk = "iface_clk",
+ {
+ .gpu_freq = 133330000,
+ .bus_freq = 0,
},
},
- .imem_clk_name = {
- .clk = "mem_clk",
- .pclk = NULL,
- },
-
+ .init_level = 0,
+ .num_levels = 2,
+ .set_grp_async = set_grp_xbar_async,
+ .idle_timeout = HZ/5,
+ .nap_allowed = false,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM,
};
struct platform_device msm_kgsl_3d0 = {
@@ -631,10 +619,10 @@
void __init msm7x25a_kgsl_3d0_init(void)
{
if (cpu_is_msm7x25a() || cpu_is_msm7x25aa()) {
- kgsl_3d0_pdata.pwr_data.pwrlevel[0].gpu_freq = 133330000;
- kgsl_3d0_pdata.pwr_data.pwrlevel[0].bus_freq = 160000000;
- kgsl_3d0_pdata.pwr_data.pwrlevel[1].gpu_freq = 96000000;
- kgsl_3d0_pdata.pwr_data.pwrlevel[1].bus_freq = 0;
+ kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 133330000;
+ kgsl_3d0_pdata.pwrlevel[0].bus_freq = 160000000;
+ kgsl_3d0_pdata.pwrlevel[1].gpu_freq = 96000000;
+ kgsl_3d0_pdata.pwrlevel[1].bus_freq = 0;
}
}
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 017eed9..41136d2 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -1102,37 +1102,27 @@
};
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 245760000,
- .bus_freq = 192000000,
- },
- {
- .gpu_freq = 192000000,
- .bus_freq = 152000000,
- },
- {
- .gpu_freq = 192000000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 245760000,
+ .bus_freq = 192000000,
},
- .init_level = 0,
- .num_levels = 3,
- .set_grp_async = set_grp3d_async,
- .idle_timeout = HZ/20,
- .nap_allowed = true,
- },
- .clk = {
- .name = {
- .clk = "core_clk",
- .pclk = "iface_clk",
+ {
+ .gpu_freq = 192000000,
+ .bus_freq = 152000000,
+ },
+ {
+ .gpu_freq = 192000000,
+ .bus_freq = 0,
},
},
- .imem_clk_name = {
- .clk = "mem_clk",
- .pclk = NULL,
- },
+ .init_level = 0,
+ .num_levels = 3,
+ .set_grp_async = set_grp3d_async,
+ .idle_timeout = HZ/20,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_SRC | KGSL_CLK_CORE |
+ KGSL_CLK_IFACE | KGSL_CLK_MEM,
};
struct platform_device msm_kgsl_3d0 = {
@@ -1161,26 +1151,19 @@
};
static struct kgsl_device_platform_data kgsl_2d0_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 0,
- .bus_freq = 192000000,
- },
- },
- .init_level = 0,
- .num_levels = 1,
- /* HW workaround, run Z180 SYNC @ 192 MHZ */
- .set_grp_async = NULL,
- .idle_timeout = HZ/10,
- .nap_allowed = true,
- },
- .clk = {
- .name = {
- .clk = "core_clk",
- .pclk = "iface_clk",
+ .pwrlevel = {
+ {
+ .gpu_freq = 0,
+ .bus_freq = 192000000,
},
},
+ .init_level = 0,
+ .num_levels = 1,
+ /* HW workaround, run Z180 SYNC @ 192 MHZ */
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/10,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE,
};
struct platform_device msm_kgsl_2d0 = {
diff --git a/arch/arm/mach-msm/devices-msm8x60.c b/arch/arm/mach-msm/devices-msm8x60.c
index 43c13bc..d89c9d7 100644
--- a/arch/arm/mach-msm/devices-msm8x60.c
+++ b/arch/arm/mach-msm/devices-msm8x60.c
@@ -653,52 +653,41 @@
};
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 266667000,
- .bus_freq = 4,
- .io_fraction = 0,
- },
- {
- .gpu_freq = 228571000,
- .bus_freq = 3,
- .io_fraction = 33,
- },
- {
- .gpu_freq = 200000000,
- .bus_freq = 2,
- .io_fraction = 100,
- },
- {
- .gpu_freq = 177778000,
- .bus_freq = 1,
- .io_fraction = 100,
- },
- {
- .gpu_freq = 27000000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 266667000,
+ .bus_freq = 4,
+ .io_fraction = 0,
},
- .init_level = 0,
- .num_levels = 5,
- .set_grp_async = NULL,
- .idle_timeout = HZ/5,
- .nap_allowed = true,
+ {
+ .gpu_freq = 228571000,
+ .bus_freq = 3,
+ .io_fraction = 33,
+ },
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 2,
+ .io_fraction = 100,
+ },
+ {
+ .gpu_freq = 177778000,
+ .bus_freq = 1,
+ .io_fraction = 100,
+ },
+ {
+ .gpu_freq = 27000000,
+ .bus_freq = 0,
+ },
},
- .clk = {
- .name = {
- .clk = "core_clk",
- .pclk = "iface_clk",
- },
+ .init_level = 0,
+ .num_levels = 5,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/5,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM_IFACE,
#ifdef CONFIG_MSM_BUS_SCALING
- .bus_scale_table = &grp3d_bus_scale_pdata,
+ .bus_scale_table = &grp3d_bus_scale_pdata,
#endif
- },
- .imem_clk_name = {
- .clk = NULL,
- .pclk = "mem_iface_clk",
- },
};
struct platform_device msm_kgsl_3d0 = {
@@ -727,33 +716,25 @@
};
static struct kgsl_device_platform_data kgsl_2d0_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 200000000,
- .bus_freq = 1,
- },
- {
- .gpu_freq = 200000000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 1,
},
- .init_level = 0,
- .num_levels = 2,
- .set_grp_async = NULL,
- .idle_timeout = HZ/10,
- .nap_allowed = true,
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 0,
+ },
},
- .clk = {
- .name = {
- /* note: 2d clocks disabled on v1 */
- .clk = "core_clk",
- .pclk = "iface_clk",
- },
+ .init_level = 0,
+ .num_levels = 2,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/10,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE,
#ifdef CONFIG_MSM_BUS_SCALING
- .bus_scale_table = &grp2d0_bus_scale_pdata,
+ .bus_scale_table = &grp2d0_bus_scale_pdata,
#endif
- },
};
struct platform_device msm_kgsl_2d0 = {
@@ -782,32 +763,25 @@
};
static struct kgsl_device_platform_data kgsl_2d1_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 200000000,
- .bus_freq = 1,
- },
- {
- .gpu_freq = 200000000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 1,
},
- .init_level = 0,
- .num_levels = 2,
- .set_grp_async = NULL,
- .idle_timeout = HZ/10,
- .nap_allowed = true,
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 0,
+ },
},
- .clk = {
- .name = {
- .clk = "gfx2d1_clk",
- .pclk = "gfx2d1_pclk",
- },
+ .init_level = 0,
+ .num_levels = 2,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/10,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE,
#ifdef CONFIG_MSM_BUS_SCALING
- .bus_scale_table = &grp2d1_bus_scale_pdata,
+ .bus_scale_table = &grp2d1_bus_scale_pdata,
#endif
- },
};
struct platform_device msm_kgsl_2d1 = {
@@ -831,8 +805,7 @@
if ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 1) &&
(SOCINFO_VERSION_MINOR(socinfo_get_version()) == 0)) {
printk(KERN_WARNING "kgsl: 2D cores disabled on 8660v1\n");
- kgsl_2d0_pdata.clk.name.clk = NULL;
- kgsl_2d1_pdata.clk.name.clk = NULL;
+ kgsl_2d0_pdata.clk_map = 0;
}
}
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 2367719..35e55ec 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -911,26 +911,17 @@
};
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 0,
- .bus_freq = 128000000,
- },
- },
- .init_level = 0,
- .num_levels = 1,
- .set_grp_async = NULL,
- .idle_timeout = HZ/5,
- },
- .clk = {
- .name = {
- .clk = "core_clk",
+ .pwrlevel = {
+ {
+ .gpu_freq = 0,
+ .bus_freq = 128000000,
},
},
- .imem_clk_name = {
- .clk = "mem_clk",
- },
+ .init_level = 0,
+ .num_levels = 1,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/5,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_MEM,
};
struct platform_device msm_kgsl_3d0 = {
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index d485cd2..12e093b 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -93,7 +93,6 @@
.pwrctrl = {
.regulator_name = "fs_gfx3d",
.irq_name = KGSL_3D0_IRQ,
- .src_clk_name = "src_clk",
},
.mutex = __MUTEX_INITIALIZER(device_3d0.dev.mutex),
.state = KGSL_STATE_INIT,
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c
index 7034fd8..dd7b1d6 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.c
+++ b/drivers/gpu/msm/kgsl_pwrctrl.c
@@ -27,6 +27,34 @@
#define UPDATE_BUSY_VAL 1000000
#define UPDATE_BUSY 50
+struct clk_pair {
+ const char *name;
+ uint map;
+};
+
+struct clk_pair clks[KGSL_MAX_CLKS] = {
+ {
+ .name = "src_clk",
+ .map = KGSL_CLK_SRC,
+ },
+ {
+ .name = "core_clk",
+ .map = KGSL_CLK_CORE,
+ },
+ {
+ .name = "iface_clk",
+ .map = KGSL_CLK_IFACE,
+ },
+ {
+ .name = "mem_clk",
+ .map = KGSL_CLK_MEM,
+ },
+ {
+ .name = "mem_iface_clk",
+ .map = KGSL_CLK_MEM_IFACE,
+ },
+};
+
void kgsl_pwrctrl_pwrlevel_change(struct kgsl_device *device,
unsigned int new_level)
{
@@ -434,49 +462,43 @@
struct platform_device *pdev =
container_of(device->parentdev, struct platform_device, dev);
struct kgsl_pwrctrl *pwr = &device->pwrctrl;
- struct kgsl_device_platform_data *pdata_dev = pdev->dev.platform_data;
- struct kgsl_device_pwr_data *pdata_pwr = &pdata_dev->pwr_data;
- const char *clk_names[KGSL_MAX_CLKS] = {pwr->src_clk_name,
- pdata_dev->clk.name.clk,
- pdata_dev->clk.name.pclk,
- pdata_dev->imem_clk_name.clk,
- pdata_dev->imem_clk_name.pclk};
+ struct kgsl_device_platform_data *pdata = pdev->dev.platform_data;
/*acquire clocks */
- for (i = 1; i < KGSL_MAX_CLKS; i++) {
- if (clk_names[i]) {
- clk = clk_get(&pdev->dev, clk_names[i]);
+ for (i = 0; i < KGSL_MAX_CLKS; i++) {
+ if (pdata->clk_map & clks[i].map) {
+ clk = clk_get(&pdev->dev, clks[i].name);
if (IS_ERR(clk))
goto clk_err;
pwr->grp_clks[i] = clk;
}
}
/* Make sure we have a source clk for freq setting */
- clk = clk_get(&pdev->dev, clk_names[0]);
- pwr->grp_clks[0] = (IS_ERR(clk)) ? pwr->grp_clks[1] : clk;
+ if (pwr->grp_clks[0] == NULL)
+ pwr->grp_clks[0] = pwr->grp_clks[1];
/* put the AXI bus into asynchronous mode with the graphics cores */
- if (pdata_pwr->set_grp_async != NULL)
- pdata_pwr->set_grp_async();
+ if (pdata->set_grp_async != NULL)
+ pdata->set_grp_async();
- if (pdata_pwr->num_levels > KGSL_MAX_PWRLEVELS) {
+ if (pdata->num_levels > KGSL_MAX_PWRLEVELS) {
KGSL_PWR_ERR(device, "invalid power level count: %d\n",
- pdata_pwr->num_levels);
+ pdata->num_levels);
result = -EINVAL;
goto done;
}
- pwr->num_pwrlevels = pdata_pwr->num_levels;
- pwr->active_pwrlevel = pdata_pwr->init_level;
- for (i = 0; i < pdata_pwr->num_levels; i++) {
+ pwr->num_pwrlevels = pdata->num_levels;
+ pwr->active_pwrlevel = pdata->init_level;
+ for (i = 0; i < pdata->num_levels; i++) {
pwr->pwrlevels[i].gpu_freq =
- (pdata_pwr->pwrlevel[i].gpu_freq > 0) ?
+ (pdata->pwrlevel[i].gpu_freq > 0) ?
clk_round_rate(pwr->grp_clks[0],
- pdata_pwr->pwrlevel[i].
+ pdata->pwrlevel[i].
gpu_freq) : 0;
pwr->pwrlevels[i].bus_freq =
- pdata_pwr->pwrlevel[i].bus_freq;
+ pdata->pwrlevel[i].bus_freq;
pwr->pwrlevels[i].io_fraction =
- pdata_pwr->pwrlevel[i].io_fraction;
+ pdata->pwrlevel[i].io_fraction;
}
/* Do not set_rate for targets in sync with AXI */
if (pwr->pwrlevels[0].gpu_freq > 0)
@@ -489,8 +511,8 @@
pwr->power_flags = 0;
- pwr->nap_allowed = pdata_pwr->nap_allowed;
- pwr->interval_timeout = pdata_pwr->idle_timeout;
+ pwr->nap_allowed = pdata->nap_allowed;
+ pwr->interval_timeout = pdata->idle_timeout;
pwr->ebi1_clk = clk_get(&pdev->dev, "bus_clk");
if (IS_ERR(pwr->ebi1_clk))
pwr->ebi1_clk = NULL;
@@ -498,15 +520,14 @@
clk_set_rate(pwr->ebi1_clk,
pwr->pwrlevels[pwr->active_pwrlevel].
bus_freq);
- if (pdata_dev->clk.bus_scale_table != NULL) {
- pwr->pcl =
- msm_bus_scale_register_client(pdata_dev->clk.
+ if (pdata->bus_scale_table != NULL) {
+ pwr->pcl = msm_bus_scale_register_client(pdata->
bus_scale_table);
if (!pwr->pcl) {
KGSL_PWR_ERR(device,
"msm_bus_scale_register_client failed: "
"id %d table %p", device->id,
- pdata_dev->clk.bus_scale_table);
+ pdata->bus_scale_table);
result = -EINVAL;
goto done;
}
@@ -529,7 +550,7 @@
clk_err:
result = PTR_ERR(clk);
KGSL_PWR_ERR(device, "clk_get(%s) failed: %d\n",
- clk_names[i], result);
+ clks[i].name, result);
done:
return result;
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.h b/drivers/gpu/msm/kgsl_pwrctrl.h
index 9bf3c0f..8b33fcd 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.h
+++ b/drivers/gpu/msm/kgsl_pwrctrl.h
@@ -52,7 +52,6 @@
unsigned int nap_allowed;
const char *regulator_name;
const char *irq_name;
- const char *src_clk_name;
s64 time;
struct kgsl_busy busy;
unsigned int restore_slumber;
diff --git a/include/linux/msm_kgsl.h b/include/linux/msm_kgsl.h
index 273850f..1f898b0 100644
--- a/include/linux/msm_kgsl.h
+++ b/include/linux/msm_kgsl.h
@@ -25,6 +25,14 @@
#define KGSL_FLAGS_RESERVED2 0x00000080
#define KGSL_FLAGS_SOFT_RESET 0x00000100
+/* Clock flags to show which clocks should be controled by a given platform */
+#define KGSL_CLK_SRC 0x00000001
+#define KGSL_CLK_CORE 0x00000002
+#define KGSL_CLK_IFACE 0x00000004
+#define KGSL_CLK_MEM 0x00000008
+#define KGSL_CLK_MEM_IFACE 0x00000010
+#define KGSL_CLK_AXI 0x00000020
+
#define KGSL_MAX_PWRLEVELS 5
#define KGSL_CONVERT_TO_MBPS(val) \
@@ -130,30 +138,15 @@
#define KGSL_2D1_REG_MEMORY "kgsl_2d1_reg_memory"
#define KGSL_2D1_IRQ "kgsl_2d1_irq"
-struct kgsl_grp_clk_name {
- const char *clk;
- const char *pclk;
-};
-
-struct kgsl_device_pwr_data {
+struct kgsl_device_platform_data {
struct kgsl_pwrlevel pwrlevel[KGSL_MAX_PWRLEVELS];
int init_level;
int num_levels;
int (*set_grp_async)(void);
unsigned int idle_timeout;
unsigned int nap_allowed;
-};
-
-struct kgsl_clk_data {
- struct kgsl_grp_clk_name name;
+ unsigned int clk_map;
struct msm_bus_scale_pdata *bus_scale_table;
-};
-
-struct kgsl_device_platform_data {
- struct kgsl_device_pwr_data pwr_data;
- struct kgsl_clk_data clk;
- /* imem_clk_name is for 3d only, not used in 2d devices */
- struct kgsl_grp_clk_name imem_clk_name;
const char *iommu_user_ctx_name;
const char *iommu_priv_ctx_name;
};