msm: kgsl: Use the new clock naming conventions effectively
Still allow the clocks a per-platform map for clock error checking,
but use a const array of their identical names.
Change-Id: If83654b4cf68b34f0cbde68021c267aceb423db8
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index e1e922e..fd3da76 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -4201,10 +4201,8 @@
if (SOCINFO_VERSION_MAJOR(soc_platform_version) == 1) {
struct kgsl_device_platform_data *kgsl_3d0_pdata =
msm_kgsl_3d0.dev.platform_data;
- kgsl_3d0_pdata->pwr_data.pwrlevel[0].gpu_freq =
- 320000000;
- kgsl_3d0_pdata->pwr_data.pwrlevel[1].gpu_freq =
- 266667000;
+ kgsl_3d0_pdata->pwrlevel[0].gpu_freq = 320000000;
+ kgsl_3d0_pdata->pwrlevel[1].gpu_freq = 266667000;
}
}
diff --git a/arch/arm/mach-msm/devices-8960.c b/arch/arm/mach-msm/devices-8960.c
index 0a300ad..2add8f9 100644
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -2052,52 +2052,41 @@
};
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 400000000,
- .bus_freq = 4,
- .io_fraction = 0,
- },
- {
- .gpu_freq = 300000000,
- .bus_freq = 3,
- .io_fraction = 33,
- },
- {
- .gpu_freq = 200000000,
- .bus_freq = 2,
- .io_fraction = 100,
- },
- {
- .gpu_freq = 128000000,
- .bus_freq = 1,
- .io_fraction = 100,
- },
- {
- .gpu_freq = 27000000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 400000000,
+ .bus_freq = 4,
+ .io_fraction = 0,
},
- .init_level = 0,
- .num_levels = 5,
- .set_grp_async = NULL,
- .idle_timeout = HZ/5,
- .nap_allowed = true,
+ {
+ .gpu_freq = 300000000,
+ .bus_freq = 3,
+ .io_fraction = 33,
+ },
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 2,
+ .io_fraction = 100,
+ },
+ {
+ .gpu_freq = 128000000,
+ .bus_freq = 1,
+ .io_fraction = 100,
+ },
+ {
+ .gpu_freq = 27000000,
+ .bus_freq = 0,
+ },
},
- .clk = {
- .name = {
- .clk = "core_clk",
- .pclk = "iface_clk",
- },
+ .init_level = 0,
+ .num_levels = 5,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/5,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM_IFACE,
#ifdef CONFIG_MSM_BUS_SCALING
- .bus_scale_table = &grp3d_bus_scale_pdata,
+ .bus_scale_table = &grp3d_bus_scale_pdata,
#endif
- },
- .imem_clk_name = {
- .clk = NULL,
- .pclk = "mem_iface_clk",
- },
.iommu_user_ctx_name = "gfx3d_user",
.iommu_priv_ctx_name = NULL,
};
@@ -2128,33 +2117,25 @@
};
static struct kgsl_device_platform_data kgsl_2d0_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 200000000,
- .bus_freq = 1,
- },
- {
- .gpu_freq = 200000000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 1,
},
- .init_level = 0,
- .num_levels = 2,
- .set_grp_async = NULL,
- .idle_timeout = HZ/10,
- .nap_allowed = true,
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 0,
+ },
},
- .clk = {
- .name = {
- /* note: 2d clocks disabled on v1 */
- .clk = "core_clk",
- .pclk = "iface_clk",
- },
+ .init_level = 0,
+ .num_levels = 2,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/10,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE,
#ifdef CONFIG_MSM_BUS_SCALING
- .bus_scale_table = &grp2d0_bus_scale_pdata,
+ .bus_scale_table = &grp2d0_bus_scale_pdata,
#endif
- },
.iommu_user_ctx_name = "gfx2d0_2d0",
.iommu_priv_ctx_name = NULL,
};
@@ -2185,32 +2166,25 @@
};
static struct kgsl_device_platform_data kgsl_2d1_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 200000000,
- .bus_freq = 1,
- },
- {
- .gpu_freq = 200000000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 1,
},
- .init_level = 0,
- .num_levels = 2,
- .set_grp_async = NULL,
- .idle_timeout = HZ/10,
- .nap_allowed = true,
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 0,
+ },
},
- .clk = {
- .name = {
- .clk = "core_clk",
- .pclk = "iface_clk",
- },
+ .init_level = 0,
+ .num_levels = 2,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/10,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE,
#ifdef CONFIG_MSM_BUS_SCALING
- .bus_scale_table = &grp2d1_bus_scale_pdata,
+ .bus_scale_table = &grp2d1_bus_scale_pdata,
#endif
- },
.iommu_user_ctx_name = "gfx2d1_2d1",
.iommu_priv_ctx_name = NULL,
};
diff --git a/arch/arm/mach-msm/devices-msm7x27.c b/arch/arm/mach-msm/devices-msm7x27.c
index 1bb9a21..0fb64dc 100644
--- a/arch/arm/mach-msm/devices-msm7x27.c
+++ b/arch/arm/mach-msm/devices-msm7x27.c
@@ -807,32 +807,22 @@
};
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
- .pwr_data = {
- /* bus_freq has been set to 160000 for power savings.
- * OEMs may modify the value at their discretion for performance
- * The appropriate maximum replacement for 160000 is:
- * msm7x2x_clock_data.max_axi_khz
- */
- .pwrlevel = {
- {
- .gpu_freq = 0,
- .bus_freq = 160000000,
- },
- },
- .init_level = 0,
- .num_levels = 1,
- .set_grp_async = NULL,
- .idle_timeout = HZ/5,
- },
- .clk = {
- .name = {
- .clk = "core_clk",
- .pclk = "iface_clk",
+ /* bus_freq has been set to 160000 for power savings.
+ * OEMs may modify the value at their discretion for performance
+ * The appropriate maximum replacement for 160000 is:
+ * msm7x2x_clock_data.max_axi_khz
+ */
+ .pwrlevel = {
+ {
+ .gpu_freq = 0,
+ .bus_freq = 160000000,
},
},
- .imem_clk_name = {
- .clk = "mem_clk",
- },
+ .init_level = 0,
+ .num_levels = 1,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/5,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM,
};
struct platform_device msm_kgsl_3d0 = {
diff --git a/arch/arm/mach-msm/devices-msm7x27a.c b/arch/arm/mach-msm/devices-msm7x27a.c
index 7008bd5..2b08098 100644
--- a/arch/arm/mach-msm/devices-msm7x27a.c
+++ b/arch/arm/mach-msm/devices-msm7x27a.c
@@ -588,34 +588,22 @@
};
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 245760000,
- .bus_freq = 200000000,
- },
- {
- .gpu_freq = 133330000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 245760000,
+ .bus_freq = 200000000,
},
- .init_level = 0,
- .num_levels = 2,
- .set_grp_async = set_grp_xbar_async,
- .idle_timeout = HZ/5,
- .nap_allowed = false,
- },
- .clk = {
- .name = {
- .clk = "core_clk",
- .pclk = "iface_clk",
+ {
+ .gpu_freq = 133330000,
+ .bus_freq = 0,
},
},
- .imem_clk_name = {
- .clk = "mem_clk",
- .pclk = NULL,
- },
-
+ .init_level = 0,
+ .num_levels = 2,
+ .set_grp_async = set_grp_xbar_async,
+ .idle_timeout = HZ/5,
+ .nap_allowed = false,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM,
};
struct platform_device msm_kgsl_3d0 = {
@@ -631,10 +619,10 @@
void __init msm7x25a_kgsl_3d0_init(void)
{
if (cpu_is_msm7x25a() || cpu_is_msm7x25aa()) {
- kgsl_3d0_pdata.pwr_data.pwrlevel[0].gpu_freq = 133330000;
- kgsl_3d0_pdata.pwr_data.pwrlevel[0].bus_freq = 160000000;
- kgsl_3d0_pdata.pwr_data.pwrlevel[1].gpu_freq = 96000000;
- kgsl_3d0_pdata.pwr_data.pwrlevel[1].bus_freq = 0;
+ kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 133330000;
+ kgsl_3d0_pdata.pwrlevel[0].bus_freq = 160000000;
+ kgsl_3d0_pdata.pwrlevel[1].gpu_freq = 96000000;
+ kgsl_3d0_pdata.pwrlevel[1].bus_freq = 0;
}
}
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 017eed9..41136d2 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -1102,37 +1102,27 @@
};
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 245760000,
- .bus_freq = 192000000,
- },
- {
- .gpu_freq = 192000000,
- .bus_freq = 152000000,
- },
- {
- .gpu_freq = 192000000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 245760000,
+ .bus_freq = 192000000,
},
- .init_level = 0,
- .num_levels = 3,
- .set_grp_async = set_grp3d_async,
- .idle_timeout = HZ/20,
- .nap_allowed = true,
- },
- .clk = {
- .name = {
- .clk = "core_clk",
- .pclk = "iface_clk",
+ {
+ .gpu_freq = 192000000,
+ .bus_freq = 152000000,
+ },
+ {
+ .gpu_freq = 192000000,
+ .bus_freq = 0,
},
},
- .imem_clk_name = {
- .clk = "mem_clk",
- .pclk = NULL,
- },
+ .init_level = 0,
+ .num_levels = 3,
+ .set_grp_async = set_grp3d_async,
+ .idle_timeout = HZ/20,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_SRC | KGSL_CLK_CORE |
+ KGSL_CLK_IFACE | KGSL_CLK_MEM,
};
struct platform_device msm_kgsl_3d0 = {
@@ -1161,26 +1151,19 @@
};
static struct kgsl_device_platform_data kgsl_2d0_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 0,
- .bus_freq = 192000000,
- },
- },
- .init_level = 0,
- .num_levels = 1,
- /* HW workaround, run Z180 SYNC @ 192 MHZ */
- .set_grp_async = NULL,
- .idle_timeout = HZ/10,
- .nap_allowed = true,
- },
- .clk = {
- .name = {
- .clk = "core_clk",
- .pclk = "iface_clk",
+ .pwrlevel = {
+ {
+ .gpu_freq = 0,
+ .bus_freq = 192000000,
},
},
+ .init_level = 0,
+ .num_levels = 1,
+ /* HW workaround, run Z180 SYNC @ 192 MHZ */
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/10,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE,
};
struct platform_device msm_kgsl_2d0 = {
diff --git a/arch/arm/mach-msm/devices-msm8x60.c b/arch/arm/mach-msm/devices-msm8x60.c
index 43c13bc..d89c9d7 100644
--- a/arch/arm/mach-msm/devices-msm8x60.c
+++ b/arch/arm/mach-msm/devices-msm8x60.c
@@ -653,52 +653,41 @@
};
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 266667000,
- .bus_freq = 4,
- .io_fraction = 0,
- },
- {
- .gpu_freq = 228571000,
- .bus_freq = 3,
- .io_fraction = 33,
- },
- {
- .gpu_freq = 200000000,
- .bus_freq = 2,
- .io_fraction = 100,
- },
- {
- .gpu_freq = 177778000,
- .bus_freq = 1,
- .io_fraction = 100,
- },
- {
- .gpu_freq = 27000000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 266667000,
+ .bus_freq = 4,
+ .io_fraction = 0,
},
- .init_level = 0,
- .num_levels = 5,
- .set_grp_async = NULL,
- .idle_timeout = HZ/5,
- .nap_allowed = true,
+ {
+ .gpu_freq = 228571000,
+ .bus_freq = 3,
+ .io_fraction = 33,
+ },
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 2,
+ .io_fraction = 100,
+ },
+ {
+ .gpu_freq = 177778000,
+ .bus_freq = 1,
+ .io_fraction = 100,
+ },
+ {
+ .gpu_freq = 27000000,
+ .bus_freq = 0,
+ },
},
- .clk = {
- .name = {
- .clk = "core_clk",
- .pclk = "iface_clk",
- },
+ .init_level = 0,
+ .num_levels = 5,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/5,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM_IFACE,
#ifdef CONFIG_MSM_BUS_SCALING
- .bus_scale_table = &grp3d_bus_scale_pdata,
+ .bus_scale_table = &grp3d_bus_scale_pdata,
#endif
- },
- .imem_clk_name = {
- .clk = NULL,
- .pclk = "mem_iface_clk",
- },
};
struct platform_device msm_kgsl_3d0 = {
@@ -727,33 +716,25 @@
};
static struct kgsl_device_platform_data kgsl_2d0_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 200000000,
- .bus_freq = 1,
- },
- {
- .gpu_freq = 200000000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 1,
},
- .init_level = 0,
- .num_levels = 2,
- .set_grp_async = NULL,
- .idle_timeout = HZ/10,
- .nap_allowed = true,
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 0,
+ },
},
- .clk = {
- .name = {
- /* note: 2d clocks disabled on v1 */
- .clk = "core_clk",
- .pclk = "iface_clk",
- },
+ .init_level = 0,
+ .num_levels = 2,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/10,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE,
#ifdef CONFIG_MSM_BUS_SCALING
- .bus_scale_table = &grp2d0_bus_scale_pdata,
+ .bus_scale_table = &grp2d0_bus_scale_pdata,
#endif
- },
};
struct platform_device msm_kgsl_2d0 = {
@@ -782,32 +763,25 @@
};
static struct kgsl_device_platform_data kgsl_2d1_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 200000000,
- .bus_freq = 1,
- },
- {
- .gpu_freq = 200000000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 1,
},
- .init_level = 0,
- .num_levels = 2,
- .set_grp_async = NULL,
- .idle_timeout = HZ/10,
- .nap_allowed = true,
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 0,
+ },
},
- .clk = {
- .name = {
- .clk = "gfx2d1_clk",
- .pclk = "gfx2d1_pclk",
- },
+ .init_level = 0,
+ .num_levels = 2,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/10,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE,
#ifdef CONFIG_MSM_BUS_SCALING
- .bus_scale_table = &grp2d1_bus_scale_pdata,
+ .bus_scale_table = &grp2d1_bus_scale_pdata,
#endif
- },
};
struct platform_device msm_kgsl_2d1 = {
@@ -831,8 +805,7 @@
if ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 1) &&
(SOCINFO_VERSION_MINOR(socinfo_get_version()) == 0)) {
printk(KERN_WARNING "kgsl: 2D cores disabled on 8660v1\n");
- kgsl_2d0_pdata.clk.name.clk = NULL;
- kgsl_2d1_pdata.clk.name.clk = NULL;
+ kgsl_2d0_pdata.clk_map = 0;
}
}
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 2367719..35e55ec 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -911,26 +911,17 @@
};
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 0,
- .bus_freq = 128000000,
- },
- },
- .init_level = 0,
- .num_levels = 1,
- .set_grp_async = NULL,
- .idle_timeout = HZ/5,
- },
- .clk = {
- .name = {
- .clk = "core_clk",
+ .pwrlevel = {
+ {
+ .gpu_freq = 0,
+ .bus_freq = 128000000,
},
},
- .imem_clk_name = {
- .clk = "mem_clk",
- },
+ .init_level = 0,
+ .num_levels = 1,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/5,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_MEM,
};
struct platform_device msm_kgsl_3d0 = {