msm: kgsl: Use the new clock naming conventions effectively
Still allow the clocks a per-platform map for clock error checking,
but use a const array of their identical names.
Change-Id: If83654b4cf68b34f0cbde68021c267aceb423db8
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>
diff --git a/arch/arm/mach-msm/devices-msm8x60.c b/arch/arm/mach-msm/devices-msm8x60.c
index 43c13bc..d89c9d7 100644
--- a/arch/arm/mach-msm/devices-msm8x60.c
+++ b/arch/arm/mach-msm/devices-msm8x60.c
@@ -653,52 +653,41 @@
};
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 266667000,
- .bus_freq = 4,
- .io_fraction = 0,
- },
- {
- .gpu_freq = 228571000,
- .bus_freq = 3,
- .io_fraction = 33,
- },
- {
- .gpu_freq = 200000000,
- .bus_freq = 2,
- .io_fraction = 100,
- },
- {
- .gpu_freq = 177778000,
- .bus_freq = 1,
- .io_fraction = 100,
- },
- {
- .gpu_freq = 27000000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 266667000,
+ .bus_freq = 4,
+ .io_fraction = 0,
},
- .init_level = 0,
- .num_levels = 5,
- .set_grp_async = NULL,
- .idle_timeout = HZ/5,
- .nap_allowed = true,
+ {
+ .gpu_freq = 228571000,
+ .bus_freq = 3,
+ .io_fraction = 33,
+ },
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 2,
+ .io_fraction = 100,
+ },
+ {
+ .gpu_freq = 177778000,
+ .bus_freq = 1,
+ .io_fraction = 100,
+ },
+ {
+ .gpu_freq = 27000000,
+ .bus_freq = 0,
+ },
},
- .clk = {
- .name = {
- .clk = "core_clk",
- .pclk = "iface_clk",
- },
+ .init_level = 0,
+ .num_levels = 5,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/5,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM_IFACE,
#ifdef CONFIG_MSM_BUS_SCALING
- .bus_scale_table = &grp3d_bus_scale_pdata,
+ .bus_scale_table = &grp3d_bus_scale_pdata,
#endif
- },
- .imem_clk_name = {
- .clk = NULL,
- .pclk = "mem_iface_clk",
- },
};
struct platform_device msm_kgsl_3d0 = {
@@ -727,33 +716,25 @@
};
static struct kgsl_device_platform_data kgsl_2d0_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 200000000,
- .bus_freq = 1,
- },
- {
- .gpu_freq = 200000000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 1,
},
- .init_level = 0,
- .num_levels = 2,
- .set_grp_async = NULL,
- .idle_timeout = HZ/10,
- .nap_allowed = true,
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 0,
+ },
},
- .clk = {
- .name = {
- /* note: 2d clocks disabled on v1 */
- .clk = "core_clk",
- .pclk = "iface_clk",
- },
+ .init_level = 0,
+ .num_levels = 2,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/10,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE,
#ifdef CONFIG_MSM_BUS_SCALING
- .bus_scale_table = &grp2d0_bus_scale_pdata,
+ .bus_scale_table = &grp2d0_bus_scale_pdata,
#endif
- },
};
struct platform_device msm_kgsl_2d0 = {
@@ -782,32 +763,25 @@
};
static struct kgsl_device_platform_data kgsl_2d1_pdata = {
- .pwr_data = {
- .pwrlevel = {
- {
- .gpu_freq = 200000000,
- .bus_freq = 1,
- },
- {
- .gpu_freq = 200000000,
- .bus_freq = 0,
- },
+ .pwrlevel = {
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 1,
},
- .init_level = 0,
- .num_levels = 2,
- .set_grp_async = NULL,
- .idle_timeout = HZ/10,
- .nap_allowed = true,
+ {
+ .gpu_freq = 200000000,
+ .bus_freq = 0,
+ },
},
- .clk = {
- .name = {
- .clk = "gfx2d1_clk",
- .pclk = "gfx2d1_pclk",
- },
+ .init_level = 0,
+ .num_levels = 2,
+ .set_grp_async = NULL,
+ .idle_timeout = HZ/10,
+ .nap_allowed = true,
+ .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE,
#ifdef CONFIG_MSM_BUS_SCALING
- .bus_scale_table = &grp2d1_bus_scale_pdata,
+ .bus_scale_table = &grp2d1_bus_scale_pdata,
#endif
- },
};
struct platform_device msm_kgsl_2d1 = {
@@ -831,8 +805,7 @@
if ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 1) &&
(SOCINFO_VERSION_MINOR(socinfo_get_version()) == 0)) {
printk(KERN_WARNING "kgsl: 2D cores disabled on 8660v1\n");
- kgsl_2d0_pdata.clk.name.clk = NULL;
- kgsl_2d1_pdata.clk.name.clk = NULL;
+ kgsl_2d0_pdata.clk_map = 0;
}
}