commit de7fa296b60c9086fa038350404975b7ee4e60c2
author Ralf Baechle <ralf@linux-mips.org> Wed Feb 21 00:10:19 2007 +0000
committer Ralf Baechle <ralf@linux-mips.org> Thu Feb 22 00:50:45 2007 +0000
tree 8e8aed9a18cafd1f07853076fab2fead0f29e958
parent 9693a85378b590cc7a4aa2db2174422585c7c8c4

[MIPS] SMP: Get smp_tune_scheduling to do something useful.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

arch/mips/kernel/smp.c

diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 0555fc5..c46e479 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -51,31 +51,14 @@
 EXPORT_SYMBOL(phys_cpu_present_map);
 EXPORT_SYMBOL(cpu_online_map);
 
+/* This happens early in bootup, can't really do it better */
 static void smp_tune_scheduling (void)
 {
 	struct cache_desc *cd = &current_cpu_data.scache;
-	unsigned long cachesize;       /* kB   */
-	unsigned long cpu_khz;
+	unsigned long cachesize = cd->linesz * cd->sets * cd->ways;
 
-	/*
-	 * Crude estimate until we actually meassure ...
-	 */
-	cpu_khz = loops_per_jiffy * 2 * HZ / 1000;
-
-	/*
-	 * Rough estimation for SMP scheduling, this is the number of
-	 * cycles it takes for a fully memory-limited process to flush
-	 * the SMP-local cache.
-	 *
-	 * (For a P5 this pretty much means we will choose another idle
-	 *  CPU almost always at wakeup time (this is due to the small
-	 *  L1 cache), on PIIs it's around 50-100 usecs, depending on
-	 *  the cache size)
-	 */
-	if (!cpu_khz)
-		return;
-
-	cachesize = cd->linesz * cd->sets * cd->ways;
+	if (cachesize > max_cache_size)
+		max_cache_size = cachesize;
 }
 
 extern void __init calibrate_delay(void);