msm: clock-pll: Update PLL enable sequences for new processes.
The PLL enable sequences across certain chipsets are
different due to differing manufacturing processes.
Update the PLL enabling sequences to reflect these
differences.
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
(cherry picked from commit 6da35d33d512b4dcb92ec68cf1df728da33e3381)
Conflicts:
arch/arm/mach-msm/clock-8960.c
Signed-off-by: Dhivya Subramanian <dthiru@codeaurora.org>
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
(cherry picked from commit 62ec83d7ee4739844746b81897615e499642da35)
Change-Id: I42738f570e40e6d73550030da7219b24ab65dc0c
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 94c733d..b0132f4 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -6447,7 +6447,10 @@
is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16);
if (!is_pll_enabled)
/* Ref clk = 27MHz and program pll14 to 480MHz */
- configure_pll(&pll14_config, &pll14_regs, 1);
+ configure_sr_pll(&pll14_config, &pll14_regs, 1);
+
+ /* Program PLL15 to 975MHz with ref clk = 27MHz */
+ configure_sr_pll(&pll15_config, &pll15_regs, 0);
/* Program PLL15 to 975MHz with ref clk = 27MHz */
configure_pll(&pll15_config, &pll15_regs, 0);
@@ -6456,7 +6459,7 @@
is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16);
if (!is_pll_enabled)
/* Ref clk = 27MHz and program pll4 to 393.2160MHz */
- configure_pll(&pll4_config_393, &pll4_regs, 1);
+ configure_sr_pll(&pll4_config_393, &pll4_regs, 1);
/* Enable PLL4 source on the LPASS Primary PLL Mux */
writel_relaxed(0x1, LCC_PRI_PLL_CLK_CTL_REG);
@@ -6474,7 +6477,7 @@
pll15_config.l = 0x21 | BVAL(31, 7, 0x600);
pll15_config.m = 0x1;
pll15_config.n = 0x3;
- configure_pll(&pll15_config, &pll15_regs, 0);
+ configure_sr_pll(&pll15_config, &pll15_regs, 0);
/* Disable AUX and BIST outputs */
writel_relaxed(0, MM_PLL3_TEST_CTL_REG);
}
diff --git a/arch/arm/mach-msm/clock-8974.c b/arch/arm/mach-msm/clock-8974.c
index e4bcfa9..6adf2d1 100644
--- a/arch/arm/mach-msm/clock-8974.c
+++ b/arch/arm/mach-msm/clock-8974.c
@@ -5322,16 +5322,16 @@
if (!(readl_relaxed(GCC_REG_BASE(GPLL0_STATUS_REG))
& gpll0_clk_src.status_mask))
- configure_pll(&gpll0_config, &gpll0_regs, 1);
+ configure_sr_hpm_lp_pll(&gpll0_config, &gpll0_regs, 1);
if (!(readl_relaxed(GCC_REG_BASE(GPLL1_STATUS_REG))
& gpll1_clk_src.status_mask))
- configure_pll(&gpll1_config, &gpll1_regs, 1);
+ configure_sr_hpm_lp_pll(&gpll1_config, &gpll1_regs, 1);
- configure_pll(&mmpll0_config, &mmpll0_regs, 1);
- configure_pll(&mmpll1_config, &mmpll1_regs, 1);
- configure_pll(&mmpll3_config, &mmpll3_regs, 0);
- configure_pll(&lpapll0_config, &lpapll0_regs, 1);
+ configure_sr_hpm_lp_pll(&mmpll0_config, &mmpll0_regs, 1);
+ configure_sr_hpm_lp_pll(&mmpll1_config, &mmpll1_regs, 1);
+ configure_sr_hpm_lp_pll(&mmpll3_config, &mmpll3_regs, 0);
+ configure_sr_hpm_lp_pll(&lpapll0_config, &lpapll0_regs, 1);
/* Enable GPLL0's aux outputs. */
regval = readl_relaxed(GCC_REG_BASE(GPLL0_USER_CTL_REG));
@@ -5489,7 +5489,7 @@
if (!virt_bases[APCS_BASE])
panic("clock-8974: Unable to ioremap APCS_GCC_CC memory!");
- clk_ops_local_pll.enable = msm8974_pll_clk_enable;
+ clk_ops_local_pll.enable = sr_hpm_lp_pll_clk_enable;
vdd_dig_reg = rpm_regulator_get(NULL, "vdd_dig");
if (IS_ERR(vdd_dig_reg))
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index 494823b..1574d9c 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -1814,14 +1814,14 @@
regval |= BIT(12);
writel_relaxed(regval, BB_PLL0_TEST_CTL_REG);
- configure_pll(&pll0_config, &pll0_regs, 1);
+ configure_sr_pll(&pll0_config, &pll0_regs, 1);
}
/* Check if PLL14 is enabled in FSM mode */
is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16);
if (!is_pll_enabled)
- configure_pll(&pll14_config, &pll14_regs, 1);
+ configure_sr_pll(&pll14_config, &pll14_regs, 1);
else if (!(readl_relaxed(BB_PLL14_MODE_REG) & BIT(20)))
WARN(1, "PLL14 enabled in non-FSM mode!\n");
diff --git a/arch/arm/mach-msm/clock-pll.c b/arch/arm/mach-msm/clock-pll.c
index d5831e2..23941d7 100644
--- a/arch/arm/mach-msm/clock-pll.c
+++ b/arch/arm/mach-msm/clock-pll.c
@@ -247,7 +247,7 @@
#define PLL_LOCKED_BIT BIT(16)
-int msm8974_pll_clk_enable(struct clk *c)
+int sr_hpm_lp_pll_clk_enable(struct clk *c)
{
unsigned long flags;
struct pll_clk *pll = to_pll_clk(c);
@@ -255,23 +255,12 @@
int ret = 0;
spin_lock_irqsave(&pll_reg_lock, flags);
- mode = readl_relaxed(PLL_MODE_REG(pll));
- /* Disable PLL bypass mode. */
- mode |= PLL_BYPASSNL;
+
+ /* Disable PLL bypass mode and de-assert reset. */
+ mode = PLL_BYPASSNL | PLL_RESET_N;
writel_relaxed(mode, PLL_MODE_REG(pll));
- /*
- * H/W requires a 5us delay between disabling the bypass and
- * de-asserting the reset. Delay 10us just to be safe.
- */
- mb();
- udelay(10);
-
- /* De-assert active-low PLL reset. */
- mode |= PLL_RESET_N;
- writel_relaxed(mode, PLL_MODE_REG(pll));
-
- /* Wait for pll to enable. */
+ /* Wait for pll to lock. */
for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) {
if (readl_relaxed(PLL_STATUS_REG(pll)) & PLL_LOCKED_BIT)
break;
@@ -453,7 +442,8 @@
.is_enabled = pll_clk_is_enabled,
};
-static void __init __set_fsm_mode(void __iomem *mode_reg)
+static void __init __set_fsm_mode(void __iomem *mode_reg,
+ u32 bias_count, u32 lock_count)
{
u32 regval = readl_relaxed(mode_reg);
@@ -463,12 +453,12 @@
/* Program bias count */
regval &= ~BM(19, 14);
- regval |= BVAL(19, 14, 0x1);
+ regval |= BVAL(19, 14, bias_count);
writel_relaxed(regval, mode_reg);
/* Program lock count */
regval &= ~BM(13, 8);
- regval |= BVAL(13, 8, 0x8);
+ regval |= BVAL(13, 8, lock_count);
writel_relaxed(regval, mode_reg);
/* Enable PLL FSM voting */
@@ -476,7 +466,7 @@
writel_relaxed(regval, mode_reg);
}
-void __init configure_pll(struct pll_config *config,
+void __init __configure_pll(struct pll_config *config,
struct pll_config_regs *regs, u32 ena_fsm_mode)
{
u32 regval;
@@ -509,8 +499,21 @@
regval &= ~config->vco_mask;
regval |= config->vco_val;
writel_relaxed(regval, PLL_CONFIG_REG(regs));
-
- /* Configure in FSM mode if necessary */
- if (ena_fsm_mode)
- __set_fsm_mode(PLL_MODE_REG(regs));
}
+
+void __init configure_sr_pll(struct pll_config *config,
+ struct pll_config_regs *regs, u32 ena_fsm_mode)
+{
+ __configure_pll(config, regs, ena_fsm_mode);
+ if (ena_fsm_mode)
+ __set_fsm_mode(PLL_MODE_REG(regs), 0x1, 0x8);
+}
+
+void __init configure_sr_hpm_lp_pll(struct pll_config *config,
+ struct pll_config_regs *regs, u32 ena_fsm_mode)
+{
+ __configure_pll(config, regs, ena_fsm_mode);
+ if (ena_fsm_mode)
+ __set_fsm_mode(PLL_MODE_REG(regs), 0x1, 0x0);
+}
+
diff --git a/arch/arm/mach-msm/clock-pll.h b/arch/arm/mach-msm/clock-pll.h
index 90f8a95..30f595b 100644
--- a/arch/arm/mach-msm/clock-pll.h
+++ b/arch/arm/mach-msm/clock-pll.h
@@ -111,7 +111,7 @@
}
int sr_pll_clk_enable(struct clk *c);
-int msm8974_pll_clk_enable(struct clk *c);
+int sr_hpm_lp_pll_clk_enable(struct clk *c);
/*
* PLL vote clock APIs
@@ -146,6 +146,8 @@
void *const __iomem *base;
};
-void __init configure_pll(struct pll_config *, struct pll_config_regs *, u32);
-
+void configure_sr_pll(struct pll_config *config, struct pll_config_regs *regs,
+ u32 ena_fsm_mode);
+void configure_sr_hpm_lp_pll(struct pll_config *config,
+ struct pll_config_regs *, u32 ena_fsm_mode);
#endif