msm: clock-pll: Update PLL enable sequences for new processes.
The PLL enable sequences across certain chipsets are
different due to differing manufacturing processes.
Update the PLL enabling sequences to reflect these
differences.
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
(cherry picked from commit 6da35d33d512b4dcb92ec68cf1df728da33e3381)
Conflicts:
arch/arm/mach-msm/clock-8960.c
Signed-off-by: Dhivya Subramanian <dthiru@codeaurora.org>
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
(cherry picked from commit 62ec83d7ee4739844746b81897615e499642da35)
Change-Id: I42738f570e40e6d73550030da7219b24ab65dc0c
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 94c733d..b0132f4 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -6447,7 +6447,10 @@
is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16);
if (!is_pll_enabled)
/* Ref clk = 27MHz and program pll14 to 480MHz */
- configure_pll(&pll14_config, &pll14_regs, 1);
+ configure_sr_pll(&pll14_config, &pll14_regs, 1);
+
+ /* Program PLL15 to 975MHz with ref clk = 27MHz */
+ configure_sr_pll(&pll15_config, &pll15_regs, 0);
/* Program PLL15 to 975MHz with ref clk = 27MHz */
configure_pll(&pll15_config, &pll15_regs, 0);
@@ -6456,7 +6459,7 @@
is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16);
if (!is_pll_enabled)
/* Ref clk = 27MHz and program pll4 to 393.2160MHz */
- configure_pll(&pll4_config_393, &pll4_regs, 1);
+ configure_sr_pll(&pll4_config_393, &pll4_regs, 1);
/* Enable PLL4 source on the LPASS Primary PLL Mux */
writel_relaxed(0x1, LCC_PRI_PLL_CLK_CTL_REG);
@@ -6474,7 +6477,7 @@
pll15_config.l = 0x21 | BVAL(31, 7, 0x600);
pll15_config.m = 0x1;
pll15_config.n = 0x3;
- configure_pll(&pll15_config, &pll15_regs, 0);
+ configure_sr_pll(&pll15_config, &pll15_regs, 0);
/* Disable AUX and BIST outputs */
writel_relaxed(0, MM_PLL3_TEST_CTL_REG);
}