msm: clock-pll: Update PLL enable sequences for new processes.
The PLL enable sequences across certain chipsets are
different due to differing manufacturing processes.
Update the PLL enabling sequences to reflect these
differences.
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
(cherry picked from commit 6da35d33d512b4dcb92ec68cf1df728da33e3381)
Conflicts:
arch/arm/mach-msm/clock-8960.c
Signed-off-by: Dhivya Subramanian <dthiru@codeaurora.org>
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
(cherry picked from commit 62ec83d7ee4739844746b81897615e499642da35)
Change-Id: I42738f570e40e6d73550030da7219b24ab65dc0c
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-pll.h b/arch/arm/mach-msm/clock-pll.h
index 90f8a95..30f595b 100644
--- a/arch/arm/mach-msm/clock-pll.h
+++ b/arch/arm/mach-msm/clock-pll.h
@@ -111,7 +111,7 @@
}
int sr_pll_clk_enable(struct clk *c);
-int msm8974_pll_clk_enable(struct clk *c);
+int sr_hpm_lp_pll_clk_enable(struct clk *c);
/*
* PLL vote clock APIs
@@ -146,6 +146,8 @@
void *const __iomem *base;
};
-void __init configure_pll(struct pll_config *, struct pll_config_regs *, u32);
-
+void configure_sr_pll(struct pll_config *config, struct pll_config_regs *regs,
+ u32 ena_fsm_mode);
+void configure_sr_hpm_lp_pll(struct pll_config *config,
+ struct pll_config_regs *, u32 ena_fsm_mode);
#endif