)]}'
{
  "commit": "e24c2d963a604d9eaa560c90371fa387d3eec8f1",
  "tree": "66be193d59dd22fac0b62980769c4f19e045b5a2",
  "parents": [
    "2311b1f2bbd36fa5f366a7448c718b2556e0f02c"
  ],
  "author": {
    "name": "David S. Miller",
    "email": "davem@davemloft.net",
    "time": "Thu Jun 02 12:55:50 2005 -0700"
  },
  "committer": {
    "name": "Greg Kroah-Hartman",
    "email": "gregkh@suse.de",
    "time": "Mon Jun 27 21:52:45 2005 -0700"
  },
  "message": "[PATCH] PCI: DMA bursting advice\n\nAfter seeing, at best, \"guesses\" as to the following kind\nof information in several drivers, I decided that we really\nneed a way for platforms to specifically give advice in this\narea for what works best with their PCI controller implementation.\n\nBasically, this new interface gives DMA bursting advice on\nPCI.  There are three forms of the advice:\n\n1) Burst as much as possible, it is not necessary to end bursts\n   on some particular boundary for best performance.\n\n2) Burst on some byte count multiple.  A DMA burst to some multiple of\n   number of bytes may be done, but it is important to end the burst\n   on an exact multiple for best performance.\n\n   The best example of this I am aware of are the PPC64 PCI\n   controllers, where if you end a burst mid-cacheline then\n   chip has to refetch the data and the IOMMU translations\n   which hurts performance a lot.\n\n3) Burst on a single byte count multiple.  Bursts shall end\n   exactly on the next multiple boundary for best performance.\n\n   Sparc64 and Alpha\u0027s PCI controllers operate this way.  They\n   disconnect any device which tries to burst across a cacheline\n   boundary.\n\n   Actually, newer sparc64 PCI controllers do not have this behavior.\n   That is why the \"pdev\" is passed into the interface, so I can\n   add code later to check which PCI controller the system is using\n   and give advice accordingly.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n",
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