msm: acpuclock-8960: Update the CPU, L2 and bus bandwidth tuples
Improve on the initial performance level mappings with ones
that provide a better balance of power and performance. These
will likely change again upon further characterization.
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-8960.c b/arch/arm/mach-msm/acpuclock-8960.c
index dab55fc..e216b78 100644
--- a/arch/arm/mach-msm/acpuclock-8960.c
+++ b/arch/arm/mach-msm/acpuclock-8960.c
@@ -202,26 +202,26 @@
#define L2_BOOT_IDX 11
static struct l2_level l2_freq_tbl[] = {
[0] = { {STBY_KHZ, QSB, 0, 0, 0x00 }, 1050000, 1050000, 0 },
- [1] = { { 384000, PLL_8, 0, 2, 0x00 }, 1050000, 1050000, 0 },
+ [1] = { { 384000, PLL_8, 0, 2, 0x00 }, 1050000, 1050000, 1 },
[2] = { { 432000, HFPLL, 2, 0, 0x20 }, 1050000, 1050000, 1 },
[3] = { { 486000, HFPLL, 2, 0, 0x24 }, 1050000, 1050000, 1 },
[4] = { { 540000, HFPLL, 2, 0, 0x28 }, 1050000, 1050000, 1 },
[5] = { { 594000, HFPLL, 1, 0, 0x16 }, 1050000, 1050000, 2 },
[6] = { { 648000, HFPLL, 1, 0, 0x18 }, 1050000, 1050000, 2 },
[7] = { { 702000, HFPLL, 1, 0, 0x1A }, 1050000, 1050000, 2 },
- [8] = { { 756000, HFPLL, 1, 0, 0x1C }, 1150000, 1150000, 3 },
+ [8] = { { 756000, HFPLL, 1, 0, 0x1C }, 1150000, 1150000, 2 },
[9] = { { 810000, HFPLL, 1, 0, 0x1E }, 1150000, 1150000, 3 },
[10] = { { 864000, HFPLL, 1, 0, 0x20 }, 1150000, 1150000, 3 },
[11] = { { 918000, HFPLL, 1, 0, 0x22 }, 1150000, 1150000, 3 },
[12] = { { 972000, HFPLL, 1, 0, 0x24 }, 1150000, 1150000, 3 },
- [13] = { { 1026000, HFPLL, 1, 0, 0x26 }, 1150000, 1150000, 3 },
+ [13] = { { 1026000, HFPLL, 1, 0, 0x26 }, 1150000, 1150000, 4 },
[14] = { { 1080000, HFPLL, 1, 0, 0x28 }, 1150000, 1150000, 4 },
[15] = { { 1134000, HFPLL, 1, 0, 0x2A }, 1150000, 1150000, 4 },
[16] = { { 1188000, HFPLL, 1, 0, 0x2C }, 1150000, 1150000, 4 },
- [17] = { { 1242000, HFPLL, 1, 0, 0x2E }, 1150000, 1150000, 4 },
- [18] = { { 1296000, HFPLL, 1, 0, 0x30 }, 1150000, 1150000, 4 },
- [19] = { { 1350000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 4 },
- [20] = { { 1404000, HFPLL, 1, 0, 0x34 }, 1150000, 1150000, 4 },
+ [17] = { { 1242000, HFPLL, 1, 0, 0x2E }, 1150000, 1150000, 5 },
+ [18] = { { 1296000, HFPLL, 1, 0, 0x30 }, 1150000, 1150000, 5 },
+ [19] = { { 1350000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 5 },
+ [20] = { { 1404000, HFPLL, 1, 0, 0x34 }, 1150000, 1150000, 5 },
[21] = { { 1458000, HFPLL, 1, 0, 0x36 }, 1150000, 1150000, 5 },
[22] = { { 1512000, HFPLL, 1, 0, 0x38 }, 1150000, 1150000, 5 },
[23] = { { 1566000, HFPLL, 1, 0, 0x3A }, 1150000, 1150000, 5 },
@@ -234,16 +234,16 @@
static struct acpu_level acpu_freq_tbl[] = {
{ 0, {STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 1050000 },
{ 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 1050000 },
- { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(2), 1050000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(3), 1050000 },
- { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(4), 1050000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(5), 1050000 },
+ { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 1050000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 1050000 },
+ { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 1050000 },
+ { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 1050000 },
{ 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 1050000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 1050000 },
- { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(8), 1150000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(9), 1150000 },
- { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(10), 1150000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(11), 1150000 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 1050000 },
+ { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(13), 1150000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(13), 1150000 },
+ { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(13), 1150000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(13), 1150000 },
{ 0, { 0 } }
};