msm_fb: hdmi: Support for 1280x1024@60Hz resolution
This change provides the support for VESA resolution for
monitors, 1280x1024@60Hz with pixel clock of 108MHz.
CRs-Fixed: 438028
Change-Id: I059cd379d4da62f4e5b72be1152dd2fe26d611f1
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 5e59992..7be143c 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -4105,6 +4105,7 @@
F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0),
F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0),
F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0),
+ F_TV(108000000, hdmi_pll, 108000000, 1, 0, 0),
F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0),
F_END
};
diff --git a/arch/arm/mach-msm/clock-dss-8960.c b/arch/arm/mach-msm/clock-dss-8960.c
index 03fed69..3bf0aa9 100644
--- a/arch/arm/mach-msm/clock-dss-8960.c
+++ b/arch/arm/mach-msm/clock-dss-8960.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -335,6 +335,22 @@
writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
break;
+ case 108000000:
+ writel_relaxed(0x08, HDMI_PHY_PLL_REFCLK_CFG);
+ writel_relaxed(0x21, HDMI_PHY_PLL_LOOP_FLT_CFG0);
+ writel_relaxed(0xF9, HDMI_PHY_PLL_LOOP_FLT_CFG1);
+ writel_relaxed(0x1C, HDMI_PHY_PLL_VCOCAL_CFG0);
+ writel_relaxed(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
+ writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
+ writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
+ writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
+ writel_relaxed(0x49, HDMI_PHY_PLL_SDM_CFG0);
+ writel_relaxed(0x49, HDMI_PHY_PLL_SDM_CFG1);
+ writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG2);
+ writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG3);
+ writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
+ break;
+
case 148500000:
/* 1080p60/1080p50 case */
writel_relaxed(0x2, HDMI_PHY_PLL_REFCLK_CFG);