msm: kgsl: Resize CP ROQ for A320/A305
The ROQ for the CP block has the instruction
prefetch space partitioned evenly between
RB, ST, IB1, and IB2. As we don't currently
use ST, and RB is used minimally, we can
reappropriate some of that space to be used
for prefetching more IB2 instructions.
This change has shown slight gains for some
benchmarks, particularly with MSAA.
Change-Id: I92e2b334fe061a236602b036140f708a83d1148e
Signed-off-by: Kevin Matlage <kmatlage@codeaurora.org>
diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c
index 5f16ff7..f6d3cad 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.c
+++ b/drivers/gpu/msm/adreno_ringbuffer.c
@@ -339,6 +339,8 @@
if (status != 0)
return status;
+ if (adreno_is_a305(adreno_dev) || adreno_is_a320(adreno_dev))
+ adreno_regwrite(device, REG_CP_QUEUE_THRESHOLDS, 0x000F0602);
rb->rptr = 0;
rb->wptr = 0;