msm: pcie: Disable secondary bus reset functionality
Setting the 'Secondary Bus Reset' bit in 'Bridge Control' register
of root complex port configuration space is causing the PCIE core to
reset due to hardware limitation. Discard any request to set this bit.
Change-Id: Iacad6ba8e8a49406428bf875901817f3f96fa24d
Signed-off-by: Niranjana Vishwanathapura <nvishwan@codeaurora.org>
diff --git a/arch/arm/mach-msm/pcie.c b/arch/arm/mach-msm/pcie.c
index f105356..d954b53 100644
--- a/arch/arm/mach-msm/pcie.c
+++ b/arch/arm/mach-msm/pcie.c
@@ -200,6 +200,16 @@
static int msm_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 val)
{
+ /*
+ *Attempt to reset secondary bus is causing PCIE core to reset.
+ *Disable secondary bus reset functionality.
+ */
+ if ((bus->number == 0) && (where == PCI_BRIDGE_CONTROL) &&
+ (val & PCI_BRIDGE_CTL_BUS_RESET)) {
+ pr_info("PCIE secondary bus reset not supported\n");
+ val &= ~PCI_BRIDGE_CTL_BUS_RESET;
+ }
+
return msm_pcie_oper_conf(bus, devfn, WR, where, size, &val);
}