msm: pil-8960: Break off Q6v4 pil code into platform driver
Create a platform driver to manage the Q6v4 instead of having
a module that exists for any 8960 target. This allows us to add
platform devices when the device really exists and simplifies how
we handle regulators as well.
Change-Id: I20956040662a8aaf331b415c2b6c6f283ec4feef
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
diff --git a/arch/arm/mach-msm/devices-8960.c b/arch/arm/mach-msm/devices-8960.c
index 2add8f9..8e1e63a 100644
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -38,6 +38,8 @@
#include "footswitch.h"
#include "msm_watchdog.h"
#include "rpm_stats.h"
+#include "pil-q6v4.h"
+#include "scm-pas.h"
#ifdef CONFIG_MSM_MPM
#include "mpm.h"
@@ -815,6 +817,107 @@
},
};
+#define MSM_LPASS_QDSP6SS_PHYS 0x28800000
+#define SFAB_LPASS_Q6_ACLK_CTL (MSM_CLK_CTL_BASE + 0x23A0)
+
+static struct resource msm_8960_q6_lpass_resources[] = {
+ {
+ .start = MSM_LPASS_QDSP6SS_PHYS,
+ .end = MSM_LPASS_QDSP6SS_PHYS + SZ_256 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct pil_q6v4_pdata msm_8960_q6_lpass_data = {
+ .strap_tcm_base = 0x01460000,
+ .strap_ahb_upper = 0x00290000,
+ .strap_ahb_lower = 0x00000280,
+ .aclk_reg = SFAB_LPASS_Q6_ACLK_CTL,
+ .name = "q6",
+ .pas_id = PAS_Q6,
+};
+
+struct platform_device msm_8960_q6_lpass = {
+ .name = "pil_qdsp6v4",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(msm_8960_q6_lpass_resources),
+ .resource = msm_8960_q6_lpass_resources,
+ .dev.platform_data = &msm_8960_q6_lpass_data,
+};
+
+#define MSM_MSS_ENABLE_PHYS 0x08B00000
+#define MSM_FW_QDSP6SS_PHYS 0x08800000
+#define MSS_Q6FW_JTAG_CLK_CTL (MSM_CLK_CTL_BASE + 0x2C6C)
+#define SFAB_MSS_Q6_FW_ACLK_CTL (MSM_CLK_CTL_BASE + 0x2044)
+
+static struct resource msm_8960_q6_mss_fw_resources[] = {
+ {
+ .start = MSM_FW_QDSP6SS_PHYS,
+ .end = MSM_FW_QDSP6SS_PHYS + SZ_256 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MSM_MSS_ENABLE_PHYS,
+ .end = MSM_MSS_ENABLE_PHYS + 4 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct pil_q6v4_pdata msm_8960_q6_mss_fw_data = {
+ .strap_tcm_base = 0x00400000,
+ .strap_ahb_upper = 0x00090000,
+ .strap_ahb_lower = 0x00000080,
+ .aclk_reg = SFAB_MSS_Q6_FW_ACLK_CTL,
+ .jtag_clk_reg = MSS_Q6FW_JTAG_CLK_CTL,
+ .name = "modem_fw",
+ .depends = "q6",
+ .pas_id = PAS_MODEM_FW,
+};
+
+struct platform_device msm_8960_q6_mss_fw = {
+ .name = "pil_qdsp6v4",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(msm_8960_q6_mss_fw_resources),
+ .resource = msm_8960_q6_mss_fw_resources,
+ .dev.platform_data = &msm_8960_q6_mss_fw_data,
+};
+
+#define MSM_SW_QDSP6SS_PHYS 0x08900000
+#define SFAB_MSS_Q6_SW_ACLK_CTL (MSM_CLK_CTL_BASE + 0x2040)
+#define MSS_Q6SW_JTAG_CLK_CTL (MSM_CLK_CTL_BASE + 0x2C68)
+
+static struct resource msm_8960_q6_mss_sw_resources[] = {
+ {
+ .start = MSM_SW_QDSP6SS_PHYS,
+ .end = MSM_SW_QDSP6SS_PHYS + SZ_256 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MSM_MSS_ENABLE_PHYS,
+ .end = MSM_MSS_ENABLE_PHYS + 4 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct pil_q6v4_pdata msm_8960_q6_mss_sw_data = {
+ .strap_tcm_base = 0x00420000,
+ .strap_ahb_upper = 0x00090000,
+ .strap_ahb_lower = 0x00000080,
+ .aclk_reg = SFAB_MSS_Q6_SW_ACLK_CTL,
+ .jtag_clk_reg = MSS_Q6SW_JTAG_CLK_CTL,
+ .name = "modem",
+ .depends = "modem_fw",
+ .pas_id = PAS_MODEM_SW,
+};
+
+struct platform_device msm_8960_q6_mss_sw = {
+ .name = "pil_qdsp6v4",
+ .id = 2,
+ .num_resources = ARRAY_SIZE(msm_8960_q6_mss_sw_resources),
+ .resource = msm_8960_q6_mss_sw_resources,
+ .dev.platform_data = &msm_8960_q6_mss_sw_data,
+};
+
struct platform_device msm_device_smd = {
.name = "msm_smd",
.id = -1,