)]}'
{
  "commit": "ebb8a4e48722c8f5e04a6490b197d2fbc894a0f6",
  "tree": "6fd92615398fae2af9ada5206f52dafde7d4e16a",
  "parents": [
    "76078dc4fc389185fe467d33428f259ea9e69807"
  ],
  "author": {
    "name": "Michael Hennerich",
    "email": "michael.hennerich@analog.com",
    "time": "Thu Aug 05 17:53:57 2010 -0400"
  },
  "committer": {
    "name": "Greg Kroah-Hartman",
    "email": "gregkh@suse.de",
    "time": "Mon Aug 23 20:50:15 2010 -0700"
  },
  "message": "USB: isp1760: use a write barrier to ensure proper ndelay timing\n\nThe ISP1760 has some timing requirements where it has to delay a short\nperiod after a write to a register has started.  However, this delay is\nfrom the time the write hits the USB chip (the ISP1760), not from the\ntime where the processor started processing the write.  So on a quick\nenough processor, it is sometimes possible for the write to not hit the\ndevice before we start delaying, and we then violate the part\u0027s timing\nrequirements, so things stop working.\n\nTo avoid all this, insert a write barrier after the register write and\nbefore the timing delay/register read so we can guarantee we only start\ncounting time after the write has hit the device.\n\nSigned-off-by: Michael Hennerich \u003cmichael.hennerich@analog.com\u003e\nSigned-off-by: Mike Frysinger \u003cvapier@gentoo.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d1a3dfc9a40873ea46df2a81668b065d105fb9cc",
      "old_mode": 33188,
      "old_path": "drivers/usb/host/isp1760-hcd.c",
      "new_id": "bdba8c5d844aa4ba099e128e1ed5f765d2ae349b",
      "new_mode": 33188,
      "new_path": "drivers/usb/host/isp1760-hcd.c"
    }
  ]
}