msm: acpuclock: Move SoC-specific data into acpuclock drivers
As part of this, hard-code any configuration values that will
not change from board-to-board inside each driver instead of
passing them through the acpuclk_soc_data struct.
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Conflicts:
arch/arm/mach-msm/acpuclock-8x50.c
diff --git a/arch/arm/mach-msm/acpuclock-8x50.c b/arch/arm/mach-msm/acpuclock-8x50.c
index be0cf5b..cde5a14 100644
--- a/arch/arm/mach-msm/acpuclock-8x50.c
+++ b/arch/arm/mach-msm/acpuclock-8x50.c
@@ -19,6 +19,7 @@
#include <linux/errno.h>
#include <linux/cpufreq.h>
#include <linux/clk.h>
+#include <linux/mfd/tps65023.h>
#include <mach/board.h>
#include <mach/msm_iomap.h>
@@ -39,6 +40,12 @@
#define SCPLL_STATUS_ADDR (MSM_SCPLL_BASE + 0x18)
#define SCPLL_FSM_CTL_EXT_ADDR (MSM_SCPLL_BASE + 0x10)
+#ifdef CONFIG_QSD_SVS
+#define TPS65023_MAX_DCDC1 1600
+#else
+#define TPS65023_MAX_DCDC1 CONFIG_QSD_PMIC_DEFAULT_DCDC1
+#endif
+
enum {
ACPU_PLL_TCXO = -1,
ACPU_PLL_0 = 0,
@@ -155,8 +162,6 @@
struct clock_state {
struct clkctl_acpu_speed *current_speed;
struct mutex lock;
- uint32_t vdd_switch_time_us;
- unsigned int max_vdd;
struct clk *ebi1_clk;
int (*acpu_set_vdd) (int mvolts);
};
@@ -238,7 +243,7 @@
regval &= ~(0x7);
writel(regval, SCPLL_CTL_ADDR);
}
- udelay(drv_state.vdd_switch_time_us);
+ udelay(62);
if (state)
pr_debug("PLL 3 Enabled\n");
@@ -624,7 +629,6 @@
skip_efuse_fixup:
iounmap(ct_csr_base);
- BUG_ON(drv_state.max_vdd == 0);
/* pll0_m_val will be 36 when PLL0 is run at 235MHz
* instead of the usual 245MHz. */
@@ -633,7 +637,7 @@
PLL0_S->acpuclk_khz = 235930;
for (i = 0; acpu_freq_tbl[i].acpuclk_khz != 0; i++) {
- if (acpu_freq_tbl[i].vdd > drv_state.max_vdd) {
+ if (acpu_freq_tbl[i].vdd > TPS65023_MAX_DCDC1) {
acpu_freq_tbl[i].acpuclk_khz = 0;
break;
}
@@ -669,20 +673,41 @@
}
#endif
+static int qsd8x50_tps65023_set_dcdc1(int mVolts)
+{
+ int rc = 0;
+#ifdef CONFIG_QSD_SVS
+ rc = tps65023_set_dcdc1_level(mVolts);
+ /*
+ * By default the TPS65023 will be initialized to 1.225V.
+ * So we can safely switch to any frequency within this
+ * voltage even if the device is not probed/ready.
+ */
+ if (rc == -ENODEV && mVolts <= CONFIG_QSD_PMIC_DEFAULT_DCDC1)
+ rc = 0;
+#else
+ /*
+ * Disallow frequencies not supported in the default PMIC
+ * output voltage.
+ */
+ if (mVolts > CONFIG_QSD_PMIC_DEFAULT_DCDC1)
+ rc = -EFAULT;
+#endif
+ return rc;
+}
+
static struct acpuclk_data acpuclk_8x50_data = {
.set_rate = acpuclk_8x50_set_rate,
.get_rate = acpuclk_8x50_get_rate,
.power_collapse_khz = POWER_COLLAPSE_KHZ,
.wait_for_irq_khz = WAIT_FOR_IRQ_KHZ,
+ .switch_time_us = 20,
};
-int __init acpuclk_8x50_init(struct acpuclk_platform_data *clkdata)
+static int __init acpuclk_8x50_init(struct acpuclk_soc_data *soc_data)
{
mutex_init(&drv_state.lock);
- acpuclk_8x50_data.switch_time_us = clkdata->acpu_switch_time_us;
- drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us;
- drv_state.max_vdd = clkdata->max_vdd;
- drv_state.acpu_set_vdd = clkdata->acpu_set_vdd;
+ drv_state.acpu_set_vdd = qsd8x50_tps65023_set_dcdc1;
drv_state.ebi1_clk = clk_get(NULL, "ebi1_acpu_clk");
BUG_ON(IS_ERR(drv_state.ebi1_clk));
@@ -710,3 +735,7 @@
#endif
return 0;
}
+
+struct acpuclk_soc_data acpuclk_8x50_soc_data __initdata = {
+ .init = acpuclk_8x50_init,
+};