)]}'
{
  "commit": "f02cbbe657939489347cbda598401a56913ffcbd",
  "tree": "0d21e68d899958e6549f908b0c715c6f37200027",
  "parents": [
    "e5a06939736277c54a68ae275433db55b99d187c"
  ],
  "author": {
    "name": "Chris Metcalf",
    "email": "cmetcalf@tilera.com",
    "time": "Tue Nov 02 12:05:10 2010 -0400"
  },
  "committer": {
    "name": "Chris Metcalf",
    "email": "cmetcalf@tilera.com",
    "time": "Wed Nov 24 13:13:49 2010 -0500"
  },
  "message": "pci root complex: support for tile architecture\n\nThis change enables PCI root complex support for TILEPro.  Unlike\nTILE-Gx, TILEPro has no support for memory-mapped I/O, so the PCI\nsupport consists of hypervisor upcalls for PIO, DMA, etc.  However,\nthe performance is fine for the devices we have tested with so far\n(1Gb Ethernet, SATA, etc.).\n\nThe \u003casm/io.h\u003e header was tweaked to be a little bit more aggressive\nabout disabling attempts to map/unmap IO port space.  The hacky\n\u003casm/pci-bridge.h\u003e header was rolled into the \u003casm/pci.h\u003e header\nand the result was simplified.  Both of the latter two headers were\npreliminary versions not meant for release before now - oh well.\n\nThere is one quirk for our TILEmpower platform, which accidentally\nnegotiates up to 5GT and needs to be kicked down to 2.5GT.\n\nSigned-off-by: Chris Metcalf \u003ccmetcalf@tilera.com\u003e\n",
  "tree_diff": [
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