msm: pil-q6v5-mss: Add memory barrier after RMB_MBA_IMAGE write
Ensure the write of the image address in the RMB_MBA_IMAGE RMB
register occurs before the writes to the QDSP6SS that releases
the Q6 processor from reset.
Change-Id: I7efbe4e0b81153cc2dc15d8ec60173008478b826
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/pil-q6v5-mss.c b/arch/arm/mach-msm/pil-q6v5-mss.c
index e279f99..62685ca 100644
--- a/arch/arm/mach-msm/pil-q6v5-mss.c
+++ b/arch/arm/mach-msm/pil-q6v5-mss.c
@@ -155,11 +155,14 @@
goto err_clks;
/* Program Image Address */
- if (drv->self_auth)
+ if (drv->self_auth) {
writel_relaxed(drv->start_addr, drv->rmb_base + RMB_MBA_IMAGE);
- else
+ /* Ensure write to RMB base occurs before reset is released. */
+ mb();
+ } else {
writel_relaxed((drv->start_addr >> 4) & 0x0FFFFFF0,
drv->reg_base + QDSP6SS_RST_EVB);
+ }
ret = pil_q6v5_reset(pil);
if (ret)