)]}'
{
  "commit": "f50b153b1966230e78034d5ab1641ca4bb5db56d",
  "tree": "9f3f0971789ca2cbb59efbd694c172804f4547cd",
  "parents": [
    "b464fce5edc08a825907e9d48a2d2f1af0393fef"
  ],
  "author": {
    "name": "Kumar Gala",
    "email": "galak@freescale.com",
    "time": "Sat Apr 16 15:24:22 2005 -0700"
  },
  "committer": {
    "name": "Linus Torvalds",
    "email": "torvalds@ppc970.osdl.org",
    "time": "Sat Apr 16 15:24:22 2005 -0700"
  },
  "message": "[PATCH] ppc32: Support 36-bit physical addressing on e500\n\nTo add support for 36-bit physical addressing on e500 the following changes\nhave been made.  The changes are generalized to support any physical address\nsize larger than 32-bits:\n\n* Allow FSL Book-E parts to use a 64-bit PTE, it is 44-bits of pfn, 20-bits\n  of flags.\n\n* Introduced new CPU feature (CPU_FTR_BIG_PHYS) to allow runtime handling of\n  updating hardware register (SPRN_MAS7) which holds the upper 32-bits of\n  physical address that will be written into the TLB.  This is useful since\n  not all e500 cores support 36-bit physical addressing.\n\n* Currently have a pass through implementation of fixup_bigphys_addr\n\n* Moved _PAGE_DIRTY in the 64-bit PTE case to free room for three additional\n  storage attributes that may exist in future FSL Book-E cores and updated\n  fault handler to copy these bits into the hardware TLBs.\n\nSigned-off-by: Kumar Gala \u003ckumar.gala@freescale.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n",
  "tree_diff": [
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