msm: acpuclock: Add 1GHz clock frequency table for 7x27AA
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock.c b/arch/arm/mach-msm/acpuclock.c
index 031725b..203e027 100644
--- a/arch/arm/mach-msm/acpuclock.c
+++ b/arch/arm/mach-msm/acpuclock.c
@@ -301,6 +301,21 @@
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
};
+/* 7x27aa pll4 at 1008mhz with GSM capable modem */
+static struct clkctl_acpu_speed pll0_960_pll1_245_pll2_1200_pll4_1008[] = {
+ { 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 30720 },
+ { 0, 61440, ACPU_PLL_1, 1, 3, 7680, 3, 1, 61440 },
+ { 1, 122880, ACPU_PLL_1, 1, 1, 15360, 3, 2, 61440 },
+ { 1, 245760, ACPU_PLL_1, 1, 0, 30720, 3, 3, 61440 },
+ { 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 4, 150000 },
+ { 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
+ { 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
+ { 0, 504000, ACPU_PLL_4, 6, 1, 63000, 3, 6, 200000 },
+ { 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 200000 },
+ { 1, 1008000, ACPU_PLL_4, 6, 0, 126000, 3, 7, 200000},
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+};
+
#define PLL_0_MHZ 0
#define PLL_196_MHZ 10
#define PLL_245_MHZ 12
@@ -308,6 +323,7 @@
#define PLL_768_MHZ 40
#define PLL_800_MHZ 41
#define PLL_960_MHZ 50
+#define PLL_1008_MHZ 52
#define PLL_1056_MHZ 55
#define PLL_1200_MHZ 62
@@ -337,6 +353,7 @@
PLL_CONFIG(960, 245, 800, 0),
PLL_CONFIG(960, 245, 1200, 800),
PLL_CONFIG(960, 196, 1200, 800),
+ PLL_CONFIG(960, 245, 1200, 1008),
{ 0, 0, 0, 0, 0 }
};
diff --git a/arch/arm/mach-msm/devices-msm7x27a.c b/arch/arm/mach-msm/devices-msm7x27a.c
index 6b87c75..6184a64 100644
--- a/arch/arm/mach-msm/devices-msm7x27a.c
+++ b/arch/arm/mach-msm/devices-msm7x27a.c
@@ -663,6 +663,9 @@
if (socinfo_init() < 0)
pr_err("%s: socinfo_init() failed!\n", __func__);
+ if (cpu_is_msm7x27aa())
+ msm7x2x_clock_data.max_speed_delta_khz = 504000;
+
msm_clock_init(msm_clocks_7x27a, msm_num_clocks_7x27a);
msm_acpu_clock_init(&msm7x2x_clock_data);