)]}'
{
  "commit": "f5f0307f42d39a51a925ca4841f76a2f2ea330ff",
  "tree": "5dbaa4b57f6726537e1fd2ba6eb7c97854d85610",
  "parents": [
    "ba00ce1d6e08ad06f19f2ac53fd5c60bbe3fbeeb"
  ],
  "author": {
    "name": "Anton Blanchard",
    "email": "anton@samba.org",
    "time": "Sun May 08 21:36:44 2011 +0000"
  },
  "committer": {
    "name": "Benjamin Herrenschmidt",
    "email": "benh@kernel.crashing.org",
    "time": "Thu May 19 14:30:42 2011 +1000"
  },
  "message": "powerpc: Improve scheduling of system call entry instructions\n\nAfter looking at our system call path, Mary Brown suggested that we\nshould put all mfspr SRR* instructions before any mtspr SRR*.\n\nTo test this I used a very simple null syscall (actually getppid)\ntestcase at http://ozlabs.org/~anton/junkcode/null_syscall.c\n\nI tested with the following changes against the pseries_defconfig:\n\nCONFIG_VIRT_CPU_ACCOUNTING\u003dn\nCONFIG_AUDIT\u003dn\n\nto remove the overhead of virtual CPU accounting and syscall\nauditing.\n\nPOWER6:\nbaseline:       mean \u003d 757.2 cycles       sd \u003d 2.108\nmodified:       mean \u003d 759.1 cycles       sd \u003d 2.020\n\nPOWER7:\nbaseline:       mean \u003d 411.4 cycles       sd \u003d 0.138\nmodified:       mean \u003d 404.1 cycles       sd \u003d 0.109\n\nSo we have 1.77% improvement on POWER7 which looks significant. The\nPOWER6 suggest a 0.25% slowdown, but the results are within 1\nstandard deviation and may be in the noise.\n\nSigned-off-by: Anton Blanchard \u003canton@samba.org\u003e\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0ec3b42717d7ea2694a069b1fa8162023e2ec136",
      "old_mode": 33188,
      "old_path": "arch/powerpc/kernel/exceptions-64s.S",
      "new_id": "a85f4874cba771fca11887ce4be593bde2c5728a",
      "new_mode": 33188,
      "new_path": "arch/powerpc/kernel/exceptions-64s.S"
    }
  ]
}