)]}'
{
  "commit": "f67f4ef5fcdfdeeddcb0ed4ab2c85d9bb4185d5f",
  "tree": "2a2dd8b027cc596dae37dd1b0a3710bca4791ef1",
  "parents": [
    "3d97a619acbb2c8a7a9a7da08c2d3041dfdd241f"
  ],
  "author": {
    "name": "Scott Wood",
    "email": "scottwood@freescale.com",
    "time": "Wed Jun 22 11:25:42 2011 +0000"
  },
  "committer": {
    "name": "Benjamin Herrenschmidt",
    "email": "benh@kernel.crashing.org",
    "time": "Wed Jun 29 17:47:48 2011 +1000"
  },
  "message": "powerpc/book3e-64: use a separate TLB handler when linear map is bolted\n\nOn MMUs such as FSL where we can guarantee the entire linear mapping is\nbolted, we don\u0027t need to worry about linear TLB misses.  If on top of\nthat we do a full table walk, we get rid of all recursive TLB faults, and\ncan dispense with some state saving.  This gains a few percent on\nTLB-miss-heavy workloads, and around 50% on a benchmark that had a high\nrate of virtual page table faults under the normal handler.\n\nWhile touching the EX_TLB layout, remove EX_TLB_MMUCR0, EX_TLB_SRR0, and\nEX_TLB_SRR1 as they\u0027re not used.\n\n[BenH: Fixed build with 64K pages (wsp config)]\n\nSigned-off-by: Scott Wood \u003cscottwood@freescale.com\u003e\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\n",
  "tree_diff": [
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    },
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      "old_path": "arch/powerpc/mm/tlb_low_64e.S",
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}