crypto: Adding crypto MSM9615.
Added the configuration settings for supporting MSM9615.
-MSM9615 does not have TZ(trust zone) hence DM configurations are done
when checking the target.
-MSM9615 does not support PMEM and hence pmem related functions are
featurized under PMEM feature - CONFIG_ANDROID_PMEM
- Added changes to Kconfig to have QCE40 built for MSM9615.
Change-Id: If2946463cc1869f5b0014c68d8e19816cedc8a3a
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 8850516..8088e44 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -309,20 +309,21 @@
config CRYPTO_DEV_QCE
tristate "Qualcomm Crypto Engine (QCE) module"
- select CRYPTO_DEV_QCE40 if ARCH_MSM8960
+ select CRYPTO_DEV_QCE40 if ARCH_MSM8960 || ARCH_MSM9615
default n
help
- This driver supports Qualcomm Crypto Engine in MSM7x30 MSM8660
- MSM8x55 and MSM8960
+ This driver supports Qualcomm Crypto Engine in MSM7x30, MSM8660
+ MSM8x55, MSM8960 and MSM9615
To compile this driver as a module, choose M here: the
For MSM7x30 MSM8660 and MSM8x55 the module is called qce
- For MSM8960 the module is called qce40
+ For MSM8960 and MSM9615 the module is called qce40
config CRYPTO_DEV_QCEDEV
tristate "QCEDEV Interface to CE module"
default n
help
- This driver supports Qualcomm QCEDEV Crypto in MSM7x30 MSM8660, MSM8960.
+ This driver supports Qualcomm QCEDEV Crypto in MSM7x30, MSM8660,
+ MSM8960 and MSM9615.
This exposes the interface to the QCE hardware accelerator via IOCTLs
To compile this driver as a module, choose M here: the
module will be called qcedev.
diff --git a/drivers/crypto/msm/qce40.c b/drivers/crypto/msm/qce40.c
index 90a7889..4ef2e08 100644
--- a/drivers/crypto/msm/qce40.c
+++ b/drivers/crypto/msm/qce40.c
@@ -29,6 +29,7 @@
#include <crypto/sha.h>
#include <mach/dma.h>
#include <mach/clk.h>
+#include <mach/socinfo.h>
#include "qce.h"
#include "qce40.h"
@@ -149,6 +150,12 @@
pce_dev->ce_dm.ce_block_size = 16;
}
}
+ /*
+ * This is a temporary change - until Data Mover changes its
+ * configuration from 16 byte crci to 64 byte crci.
+ */
+ if (cpu_is_msm9615())
+ pce_dev->ce_dm.ce_block_size = 16;
dev_info(pce_dev->pdev,
"IO base 0x%x\n, ce_in channel %d , "
@@ -161,6 +168,23 @@
return 0;
};
+#ifdef CONFIG_ARCH_MSM9615
+static void config_ce_engine(struct qce_device *pce_dev)
+{
+ unsigned int val = 0;
+
+ val = (1 << CRYPTO_MASK_DOUT_INTR) | (1 << CRYPTO_MASK_DIN_INTR) |
+ (1 << CRYPTO_MASK_OP_DONE_INTR) |
+ (1 << CRYPTO_MASK_ERR_INTR);
+
+ writel_relaxed(val, pce_dev->iobase + CRYPTO_CONFIG_REG);
+}
+#else
+static void config_ce_engine(struct qce_device *pce_dev)
+{
+
+}
+#endif
static void _check_probe_done_call_back(struct msm_dmov_cmd *cmd_ptr,
unsigned int result, struct msm_dmov_errdata *err)
@@ -185,6 +209,22 @@
clk_reset(pce_dev->ce_core_clk, CLK_RESET_ASSERT);
clk_reset(pce_dev->ce_core_clk, CLK_RESET_DEASSERT);
+ /*
+ * Ensure previous instruction (any writes to CLK registers)
+ * to toggle the CLK reset lines was completed before configuring
+ * ce engine. The ce engine configuration settings should not be lost
+ * becasue of clk reset.
+ */
+ mb();
+
+ /* Configure the CE Engine */
+ config_ce_engine(pce_dev);
+
+ /*
+ * Ensure ce configuration is completed.
+ */
+ mb();
+
pce_dev->ce_dm.chan_ce_in_cmd->complete_func =
_check_probe_done_call_back;
pce_dev->ce_dm.chan_ce_in_cmd->cmdptr =
@@ -2529,4 +2569,4 @@
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Mona Hossain <mhossain@codeaurora.org>");
MODULE_DESCRIPTION("Crypto Engine driver");
-MODULE_VERSION("2.11");
+MODULE_VERSION("2.12");
diff --git a/drivers/crypto/msm/qcedev.c b/drivers/crypto/msm/qcedev.c
index dcc98a0..9d315d2 100644
--- a/drivers/crypto/msm/qcedev.c
+++ b/drivers/crypto/msm/qcedev.c
@@ -1229,6 +1229,7 @@
return qcedev_hmac_final(areq, handle);
}
+#ifdef CONFIG_ANDROID_PMEM
static int qcedev_pmem_ablk_cipher_max_xfer(struct qcedev_async_req *areq,
struct qcedev_handle *handle)
{
@@ -1438,6 +1439,18 @@
return err;
}
+#else
+static int qcedev_pmem_ablk_cipher_max_xfer(struct qcedev_async_req *areq,
+ struct qcedev_handle *handle)
+{
+ return -EPERM;
+}
+static int qcedev_pmem_ablk_cipher(struct qcedev_async_req *qcedev_areq,
+ struct qcedev_handle *handle)
+{
+ return -EPERM;
+}
+#endif/*CONFIG_ANDROID_PMEM*/
static int qcedev_vbuf_ablk_cipher_max_xfer(struct qcedev_async_req *areq,
int *di, struct qcedev_handle *handle,
@@ -1837,7 +1850,7 @@
podev))
return -EINVAL;
- if (qcedev_areq.cipher_op_req.use_pmem == QCEDEV_USE_PMEM)
+ if ((qcedev_areq.cipher_op_req.use_pmem) && (QCEDEV_USE_PMEM))
err = qcedev_pmem_ablk_cipher(&qcedev_areq, handle);
else
err = qcedev_vbuf_ablk_cipher(&qcedev_areq, handle);
@@ -2156,7 +2169,7 @@
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Mona Hossain <mhossain@codeaurora.org>");
MODULE_DESCRIPTION("Qualcomm DEV Crypto driver");
-MODULE_VERSION("1.23");
+MODULE_VERSION("1.24");
module_init(qcedev_init);
module_exit(qcedev_exit);