)]}'
{
  "commit": "fb702b942bf638baa6cbbbda9f76794db62921ef",
  "tree": "c065b0ab61cbb80b6209c725836a6864624b3c46",
  "parents": [
    "de5d9bf6541736dc7ad264d2b5cc99bc1b2ad958"
  ],
  "author": {
    "name": "Chris Metcalf",
    "email": "cmetcalf@tilera.com",
    "time": "Fri Jun 25 16:41:11 2010 -0400"
  },
  "committer": {
    "name": "Chris Metcalf",
    "email": "cmetcalf@tilera.com",
    "time": "Tue Jul 06 13:34:01 2010 -0400"
  },
  "message": "arch/tile: Enable more sophisticated IRQ model for 32-bit chips.\n\nThis model is based on the on-chip interrupt model used by the\nTILE-Gx next-generation hardware, and interacts much more cleanly\nwith the Linux generic IRQ layer.\n\nThe change includes modifications to the Tilera hypervisor, which\nare reflected in the hypervisor headers in arch/tile/include/arch/.\n\nSigned-off-by: Chris Metcalf \u003ccmetcalf@tilera.com\u003e\nAcked-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n",
  "tree_diff": [
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