msm: acpuclock-8930ab: Update PVS Data for 1.7 GHZ parts
Characterization has been performed for 1.7GHz parts.
Add seven PVS tables and eliminate unused frequencies.
Change-Id: Ic5b738c85ba3032904c7882d7b25e6c0bd557828
Signed-off-by: Uma Maheshwari Bhiram <ubhira@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-8930ab.c b/arch/arm/mach-msm/acpuclock-8930ab.c
index 5003862..55de66a 100644
--- a/arch/arm/mach-msm/acpuclock-8930ab.c
+++ b/arch/arm/mach-msm/acpuclock-8930ab.c
@@ -151,101 +151,140 @@
{ }
};
-static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
+static struct acpu_level tbl_PVS0_1700MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 1000000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 1000000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1075000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1100000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1125000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1200000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1225000 },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1237500 },
- { 0, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1250000 },
- { 0, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1262500 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1262500 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1287500 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1050000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1075000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1100000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1125000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1150000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1175000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1200000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1225000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1250000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1275000 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
+static struct acpu_level tbl_PVS1_1700MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 975000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1075000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1100000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1125000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1200000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1225000 },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1237500 },
- { 0, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1250000 },
- { 0, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1262500 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1262500 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1287500 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1000000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1025000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1050000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1075000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1100000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1125000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1150000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1175000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1200000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1225000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1250000 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
+static struct acpu_level tbl_PVS2_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1075000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1100000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1125000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1200000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1225000 },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1237500 },
- { 0, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1250000 },
- { 0, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1262500 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1262500 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1287500 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 975000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1000000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1025000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1050000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1075000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1100000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1125000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1150000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1175000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1200000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1225000 },
{ 0, { 0 } }
};
-/* TODO: Update boost voltage once the pvs data is available */
+static struct acpu_level tbl_PVS3_1700MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 950000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 975000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1000000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1025000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1050000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1075000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1100000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1125000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1150000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1175000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1200000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level tbl_PVS4_1700MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 950000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 975000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1000000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1025000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1050000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1075000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1100000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1125000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1150000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1175000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level tbl_PVS5_1700MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 925000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 950000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 975000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1000000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1025000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1050000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1075000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1100000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1125000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1150000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level tbl_PVS6_1700MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 900000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 925000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 950000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 975000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1000000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1025000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1050000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1075000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1100000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1125000 },
+ { 0, { 0 } }
+};
+
static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = {
-[0][PVS_SLOW] = { acpu_freq_tbl_slow, sizeof(acpu_freq_tbl_slow), 0 },
-[0][PVS_NOMINAL] = { acpu_freq_tbl_nom, sizeof(acpu_freq_tbl_nom), 25000 },
-[0][PVS_FAST] = { acpu_freq_tbl_fast, sizeof(acpu_freq_tbl_fast), 25000 },
+ [0][0] = { tbl_PVS0_1700MHz, sizeof(tbl_PVS0_1700MHz), 0 },
+ [0][1] = { tbl_PVS1_1700MHz, sizeof(tbl_PVS1_1700MHz), 25000 },
+ [0][2] = { tbl_PVS2_1700MHz, sizeof(tbl_PVS2_1700MHz), 25000 },
+ [0][3] = { tbl_PVS3_1700MHz, sizeof(tbl_PVS3_1700MHz), 25000 },
+ [0][4] = { tbl_PVS4_1700MHz, sizeof(tbl_PVS4_1700MHz), 25000 },
+ [0][5] = { tbl_PVS5_1700MHz, sizeof(tbl_PVS5_1700MHz), 25000 },
+ [0][6] = { tbl_PVS6_1700MHz, sizeof(tbl_PVS6_1700MHz), 25000 },
};
static struct acpuclk_krait_params acpuclk_8930ab_params __initdata = {