/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef MSM_GEMINI_HW_REG_H
#define MSM_GEMINI_HW_REG_H

#define GEMINI_REG_BASE 0

#define MSM_GEMINI_HW_IRQ_MASK_ADDR 0x00000014
#define MSM_GEMINI_HW_IRQ_MASK_RMSK 0xffffffff
#define MSM_GEMINI_HW_IRQ_MASK_SHFT 0
#define MSM_GEMINI_HW_IRQ_DISABLE 0
#define MSM_GEMINI_HW_IRQ_ENABLE 0xffffffff

#define MSM_GEMINI_HW_IRQ_CLEAR_ADDR 0x00000018
#define MSM_GEMINI_HW_IRQ_CLEAR_RMSK 0xffffffff
#define MSM_GEMINI_HW_IRQ_CLEAR_SHFT 0
#define MSM_GEMINI_HW_IRQ_CLEAR  0xffffffff

#define MSM_GEMINI_HW_IRQ_STATUS_FRAMEDONE_MASK 0x00000001
#define MSM_GEMINI_HW_IRQ_STATUS_FRAMEDONE_SHIFT 0x00000000

#define MSM_GEMINI_HW_IRQ_STATUS_FE_RD_DONE_MASK 0x00000002
#define MSM_GEMINI_HW_IRQ_STATUS_FE_RD_DONE_SHIFT 0x00000001

#define MSM_GEMINI_HW_IRQ_STATUS_FE_RTOVF_MASK 0x00000004
#define MSM_GEMINI_HW_IRQ_STATUS_FE_RTOVF_SHIFT 0x00000002

#define MSM_GEMINI_HW_IRQ_STATUS_FE_VFE_OVERFLOW_MASK 0x00000008
#define MSM_GEMINI_HW_IRQ_STATUS_FE_VFE_OVERFLOW_SHIFT 0x00000003

#define MSM_GEMINI_HW_IRQ_STATUS_WE_Y_PINGPONG_MASK 0x00000010
#define MSM_GEMINI_HW_IRQ_STATUS_WE_Y_PINGPONG_SHIFT 0x00000004

#define MSM_GEMINI_HW_IRQ_STATUS_WE_CBCR_PINGPONG_MASK 0x00000020
#define MSM_GEMINI_HW_IRQ_STATUS_WE_CBCR_PINGPONG_SHIFT 0x00000005

#define MSM_GEMINI_HW_IRQ_STATUS_WE_Y_BUFFER_OVERFLOW_MASK 0x00000040
#define MSM_GEMINI_HW_IRQ_STATUS_WE_Y_BUFFER_OVERFLOW_SHIFT 0x00000006

#define MSM_GEMINI_HW_IRQ_STATUS_WE_CBCR_BUFFER_OVERFLOW_MASK 0x00000080
#define MSM_GEMINI_HW_IRQ_STATUS_WE_CBCR_BUFFER_OVERFLOW_SHIFT 0x00000007

#define MSM_GEMINI_HW_IRQ_STATUS_WE_CH0_DATAFIFO_OVERFLOW_MASK 0x00000100
#define MSM_GEMINI_HW_IRQ_STATUS_WE_CH0_DATAFIFO_OVERFLOW_SHIFT 0x00000008

#define MSM_GEMINI_HW_IRQ_STATUS_WE_CH1_DATAFIFO_OVERFLOW_MASK 0x00000200
#define MSM_GEMINI_HW_IRQ_STATUS_WE_CH1_DATAFIFO_OVERFLOW_SHIFT 0x00000009

#define MSM_GEMINI_HW_IRQ_STATUS_RESET_ACK_MASK 0x00000400
#define MSM_GEMINI_HW_IRQ_STATUS_RESET_ACK_SHIFT 0x0000000a

#define MSM_GEMINI_HW_IRQ_STATUS_BUS_ERROR_MASK 0x00000800
#define MSM_GEMINI_HW_IRQ_STATUS_BUS_ERROR_SHIFT 0x0000000b

#define MSM_GEMINI_HW_IRQ_STATUS_VIOLATION_MASK 0x00001000
#define MSM_GEMINI_HW_IRQ_STATUS_VIOLATION_SHIFT 0x0000000c

#define JPEG_BUS_CMD_HALT_REQ 0x00000001

#define JPEG_REALTIME_CMD_STOP_FB 0x00000000
#define JPEG_REALTIME_CMD_STOP_IM 0x00000003
#define JPEG_REALTIME_CMD_START 0x00000001

#define JPEG_OFFLINE_CMD_START 0x00000003

#define JPEG_DMI_CFG_DISABLE 0x00000000
#define JPEG_DMI_ADDR_START 0x00000000

#define JPEG_FE_CMD_BUFFERRELOAD 0x00000001

#define JPEG_WE_YUB_ENCODE 0x01ff0000

#define JPEG_RESET_DEFAULT 0x0004ffff /* cfff? */

#define JPEG_IRQ_DISABLE_ALL 0x00000000
#define JPEG_IRQ_CLEAR_ALL 0xffffffff
#define JPEG_IRQ_ALLSOURCES_ENABLE 0xffffffff

#define HWIO_JPEG_FE_BUFFER_CFG_ADDR (GEMINI_REG_BASE + 0x00000080)
#define HWIO_JPEG_FE_BUFFER_CFG_RMSK 0x1fff1fff

#define HWIO_JPEG_FE_Y_PING_ADDR_ADDR (GEMINI_REG_BASE + 0x00000084)
#define HWIO_JPEG_FE_Y_PING_ADDR_RMSK 0xffffffff

#define HWIO_JPEG_FE_Y_PONG_ADDR_ADDR (GEMINI_REG_BASE + 0x00000088)
#define HWIO_JPEG_FE_Y_PONG_ADDR_RMSK 0xffffffff

#define HWIO_JPEG_FE_CBCR_PING_ADDR_ADDR (GEMINI_REG_BASE + 0x0000008c)
#define HWIO_JPEG_FE_CBCR_PING_ADDR_RMSK 0xffffffff

#define HWIO_JPEG_FE_CBCR_PONG_ADDR_ADDR (GEMINI_REG_BASE + 0x00000090)
#define HWIO_JPEG_FE_CBCR_PONG_ADDR_RMSK 0xffffffff

#define HWIO_JPEG_FE_CMD_ADDR (GEMINI_REG_BASE + 0x00000094)
#define HWIO_JPEG_FE_CMD_RMSK 0x3

#define HWIO_JPEG_FE_BUFFER_CFG_CBCR_MCU_ROWS_BMSK 0x1fff0000
#define HWIO_JPEG_FE_BUFFER_CFG_CBCR_MCU_ROWS_SHFT 0x10
#define HWIO_JPEG_FE_BUFFER_CFG_Y_MCU_ROWS_BMSK 0x1fff
#define HWIO_JPEG_FE_BUFFER_CFG_Y_MCU_ROWS_SHFT 0

#define HWIO_JPEG_FE_Y_PING_ADDR_FE_Y_PING_START_ADDR_BMSK 0xffffffff
#define HWIO_JPEG_FE_Y_PING_ADDR_FE_Y_PING_START_ADDR_SHFT 0

#define HWIO_JPEG_FE_CBCR_PING_ADDR_FE_CBCR_PING_START_ADDR_BMSK 0xffffffff
#define HWIO_JPEG_FE_CBCR_PING_ADDR_FE_CBCR_PING_START_ADDR_SHFT 0

#define HWIO_JPEG_FE_Y_PONG_ADDR_FE_Y_PONG_START_ADDR_BMSK 0xffffffff
#define HWIO_JPEG_FE_Y_PONG_ADDR_FE_Y_PONG_START_ADDR_SHFT 0

#define HWIO_JPEG_FE_CBCR_PONG_ADDR_FE_CBCR_PONG_START_ADDR_BMSK 0xffffffff
#define HWIO_JPEG_FE_CBCR_PONG_ADDR_FE_CBCR_PONG_START_ADDR_SHFT 0

#define HWIO_JPEG_WE_Y_THRESHOLD_ADDR (GEMINI_REG_BASE + 0x000000c0)
#define HWIO_JPEG_WE_Y_THRESHOLD_RMSK 0x1ff01ff

#define HWIO_JPEG_WE_CBCR_THRESHOLD_ADDR (GEMINI_REG_BASE      + 0x000000c4)
#define HWIO_JPEG_WE_CBCR_THRESHOLD_RMSK 0x1ff01ff

#define HWIO_JPEG_WE_Y_UB_CFG_ADDR (GEMINI_REG_BASE + 0x000000e8)
#define HWIO_JPEG_WE_Y_UB_CFG_RMSK 0x1ff01ff

#define HWIO_JPEG_WE_Y_THRESHOLD_WE_DEASSERT_STALL_TH_BMSK 0x1ff0000
#define HWIO_JPEG_WE_Y_THRESHOLD_WE_DEASSERT_STALL_TH_SHFT 0x10
#define HWIO_JPEG_WE_Y_THRESHOLD_WE_ASSERT_STALL_TH_BMSK 0x1ff
#define HWIO_JPEG_WE_Y_THRESHOLD_WE_ASSERT_STALL_TH_SHFT 0

#define HWIO_JPEG_WE_CBCR_THRESHOLD_WE_DEASSERT_STALL_TH_BMSK 0x1ff0000
#define HWIO_JPEG_WE_CBCR_THRESHOLD_WE_DEASSERT_STALL_TH_SHFT 0x10
#define HWIO_JPEG_WE_CBCR_THRESHOLD_WE_ASSERT_STALL_TH_BMSK 0x1ff
#define HWIO_JPEG_WE_CBCR_THRESHOLD_WE_ASSERT_STALL_TH_SHFT 0

#define HWIO_JPEG_WE_Y_PING_BUFFER_CFG_ADDR (GEMINI_REG_BASE + 0x000000c8)
#define HWIO_JPEG_WE_Y_PING_BUFFER_CFG_RMSK 0x7fffff

#define HWIO_JPEG_WE_Y_PING_ADDR_ADDR (GEMINI_REG_BASE + 0x000000d8)
#define HWIO_JPEG_WE_Y_PING_ADDR_RMSK 0xfffffff8

#define HWIO_JPEG_WE_Y_PONG_BUFFER_CFG_ADDR (GEMINI_REG_BASE + 0x000000cc)
#define HWIO_JPEG_WE_Y_PONG_BUFFER_CFG_RMSK 0x7fffff

#define HWIO_JPEG_WE_Y_PONG_ADDR_ADDR (GEMINI_REG_BASE + 0x000000dc)
#define HWIO_JPEG_WE_Y_PONG_ADDR_RMSK 0xfffffff8

#define HWIO_JPEG_WE_Y_PING_BUFFER_CFG_WE_BUFFER_LENGTH_BMSK 0x7fffff
#define HWIO_JPEG_WE_Y_PING_BUFFER_CFG_WE_BUFFER_LENGTH_SHFT 0

#define HWIO_JPEG_WE_Y_PONG_BUFFER_CFG_WE_BUFFER_LENGTH_BMSK 0x7fffff
#define HWIO_JPEG_WE_Y_PONG_BUFFER_CFG_WE_BUFFER_LENGTH_SHFT 0

#define HWIO_JPEG_IRQ_MASK_ADDR (GEMINI_REG_BASE + 0x00000014)
#define HWIO_JPEG_IRQ_MASK_RMSK 0xffffffff

#define HWIO_JPEG_IRQ_CLEAR_ADDR (GEMINI_REG_BASE + 0x00000018)
#define HWIO_JPEG_IRQ_CLEAR_RMSK 0xffffffff

#define HWIO_JPEG_RESET_CMD_ADDR (GEMINI_REG_BASE + 0x00000004)
#define HWIO_JPEG_RESET_CMD_RMSK 0xe004ffff

#define HWIO_JPEG_IRQ_STATUS_ADDR (GEMINI_REG_BASE + 0x0000001c)
#define HWIO_JPEG_IRQ_STATUS_RMSK 0xffffffff

#define HWIO_JPEG_STATUS_ENCODE_OUTPUT_SIZE_ADDR (GEMINI_REG_BASE + 0x00000034)
#define HWIO_JPEG_STATUS_ENCODE_OUTPUT_SIZE_RMSK 0xffffffff

#endif /* MSM_GEMINI_HW_REG_H */
